Pin number reduction circuit and methodology for...

Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage

Reexamination Certificate

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Reexamination Certificate

active

07436246

ABSTRACT:
The pin number reduction circuit circuits and methodology of the present invention provide a higher pseudo power supply and a lower pseudo power supply for a digital functional section in mixed-signal IC, memory IC, and SOC including analog functional section and digital (or memory) functional section in order to reduce digital noise coupling. The circuit and methodology of the present invention basically includes resistors, capacitors, transistors, and amplifiers. It is noted that analog functional section is coupled between a positive power supply and a negative power supply, which are connected to two pins.One amplifier with a PMOS transistor and one resistor string provides a higher pseudo power supply, and the other amplifier with an NMOS transistor and the other resistor string provides a lower pseudo power supply so that a digital functional section is coupled between these pseudo power supplies. Furthermore, the methodology provides multiple higher pseudo power supplies and multiple lower pseudo power supplies for multiple digital (or memory) functional sections to reduce a great number of pins by dividing a complex system into modules based on well-define function, interface, and power dissipation.

REFERENCES:
patent: 6531914 (2003-03-01), Kawakubo
patent: 6542026 (2003-04-01), Wu et al.
patent: 7030686 (2006-04-01), Itoh

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