1988-07-15
1989-12-12
Davie, James W.
357 72, H01L 2302
Patent
active
048871486
ABSTRACT:
A pin grid array package structure includes a package body member (12), a wiring board (14) having a central portion for receiving a semiconductor chip (18), a tape lead circuit (16), and a cover member (22). A plurality of metal terminal pins (24) extend substantially over the entire top and bottom surfaces of the body member (12). The terminal pins extend from a bottom surface of the body member (12) and protrude slightly above a top surface thereof to form terminal pin ends (30). The wiring board (14) is placed over the body member (12) for engagement with the terminal pin ends (30). The wiring board (14) has a metalized trace pattern deposited on its top surface. The wiring board further includes an outer lead bonding area (34a) of a rectangular shape which is disposed in spaced apart surrounding relationship with the chip (18). The outer lead bonding area (34a) is formed with bonding pads (42a). The metalized trace pattern includes a plurality of conductor runs (40) terminating at its outer ends with spaced apart metal terminal pads (36) which are in substantially vertical alignment with the respective terminal pin ends (30). The plurality of conductor runs (40) are formed of first conductor runs (40a) extending outwardly from the bonding pads (42a) on the outer lead bond area (34a) and alternating second conductor runs (40a) extending inwardly from the bonding pads (42a) on the outer lead bond area (34a). The cover member encloses the body member, tape circuit, die and wiring board to prevent exposure to atmospheric environment.
REFERENCES:
patent: 4812897 (1989-03-01), Narita et al.
patent: 4823234 (1989-04-01), Konishi et al.
Advanced Micro Devices , Inc.
Chin Davis
Davie James W.
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