Pin driver for AC and DC semiconductor device testing

Details Pin driver for AC and DC semiconductor device testing Pin driver for AC and DC semiconductor device testing

2002-12-18

2004-12-28

Tang, Minh N. (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S073100, C324S1540PB

Reexamination Certificate

active

06836136

ABSTRACT:

FIELD OF THE INVENTION
The invention relates generally to automatic test equipment, and more particularly to pin electronics circuits for automatic test equipment applications.
BACKGROUND OF THE INVENTION
Automatic test equipment plays a key role in the manufacture of semiconductor devices. More commonly called “testers”, the equipment allows manufacturers to test each device for engineering characterization and/or production validation. Ensuring that every device entering commerce “works” is critical for the continued success of a semiconductor device manufacturer.
Unfortunately for the device manufacturer, test comes at a price. Typically, the more complex the device-under-test (DUT), the higher the cost to test it. Cost of test is one of the more important factors in deciding the type of tester to employ in the factory.
Much of the cost of a semiconductor tester is wrapped into the channel architecture. A channel may be thought of as the electronic resources in the tester that interface with one pin of the device-under-test (DUT). If the DUT pins require high performance and high accuracy test signals in order to adequately test the part, each channel may require a host of costly enabling features to achieve the performance. On the other hand, a channel architecture may be greatly simplified, and less costly, if the performance parameters are low.
Typically, as shown generally in
FIG. 1
, the conventional channel architecture for a semiconductor tester includes AC test circuitry in the form of an AC driver
10
responsive to a pattern generator
12
, and DC test circuitry including a DC parametric measurement unit
14
. Generally, the AC driver generates and drives AC and test waveforms along a transmission line
16
to a DUT
18
, while the DC test circuitry forces a DC voltage or current to the DUT and performs various DC measurements. Usually, tests are performed on the tester at separate times.
Referring now to
FIG. 2
, which illustrates the conventional channel architecture in further detail, the AC driver circuitry
10
couples to the DUT
18
via the transmission line
16
with a complementing comparator circuit
20
. The comparator circuit captures signals from the DUT
18
that are generated in response to the AC driver waveforms. The captured signals are then compared to expected signals to determine whether the DUT functioned as expected.
Further referring to
FIG. 2
, the DC test circuitry
14
comprises a separate circuit known as a per-pin-parametric-unit, or PPMU. The unit employs an amplifier
22
responsive to a multiplexer
24
that selectively provides one of two DC levels Vin
1
(a forcing voltage level) or Vin
2
(a “safe” voltage such as ground). A register
26
provides the control signal input to the multiplexer. Disposed at the output of the amplifier is a current measuring circuit comprising a second amplifier
28
with a current sense resistor R. In general, the PPMU provides a force/measurement functionality for DC voltage and current testing of the DUT
18
. Consequently, because of its inherent DC characteristics, the PPMU is typically a low-cost circuit.
While this general architecture works well for its intended applications, the cost and size of the hardware to realize the separate AC and DC driver circuits
10
and
14
is often prohibitive for very low-cost and low-performance testers, such as design-for-test (DFT) testers. Thus, the need exists for a low-cost channel architecture for low-cost and low-performance testers. The pin driver circuit of the present invention satisfies these needs.
SUMMARY OF THE INVENTION
The pin driver circuit of the present invention provides a cost effective way to achieve AC and DC tests and reduce the cost of support circuitry, such as level generation circuitry. Tester board area optimization is also realized. This is accomplished by modifying a conventional PPMU circuit to enable dual AC and DC test functionality.
To realize the foregoing advantages, the invention in one form comprises a pin electronics circuit for use in automatic test equipment. The pin electronics circuit includes a pin driver having an output adapted for coupling to a device-under-test pin, and a first input. AC input circuitry couples to a pattern generator to receive pattern test signals while DC input circuitry connects to a DC parametric controller. Selector circuitry selectively couples the AC and DC input circuitry to the pin driver first input.
In another form, the invention comprises a method of applying test signals with a pin driver to a semiconductor device pin. The method includes the steps of: (a) selecting an AC test mode; (b) conducting the AC test by applying AC signals to the pin driver to generate AC output test signals from the pin driver, and driving the AC output test signals from the pin driver to the device pin. The method continues by (c) selecting a DC test mode, (d) conducting the DC test by performing DC parametric measurements on the device-under-test.
In a further form, the invention comprises a pin electronics circuit for use in automatic test equipment. The pin electronics circuit includes means for driving test waveforms to a device-under-test pin, the means for driving having an output for coupling to the pin, and an input. AC input circuitry means couples to a pattern generator to receive pattern test signals while DC input circuitry means connects to a DC parametric controller. The pin electronics circuit further includes means for selectively coupling the AC and DC input circuitry means to the means for driving input.
Other features and advantages of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.


REFERENCES:
patent: 4517512 (1985-05-01), Petrich et al.
patent: 5101153 (1992-03-01), Morong, III
patent: 5467024 (1995-11-01), Swapp
patent: 6404220 (2002-06-01), Hashimoto

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