Pin block structure for mounting contact pins

Details Pin block structure for mounting contact pins Pin block structure for mounting contact pins

1999-09-14

2001-06-26

Karlsen, Ernest (Department: 2858)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S754090, C324S758010

Reexamination Certificate

active

06252415

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to a pin block structure for mounting a large number of contact pins to be used for testing semiconductor devices, and more particularly, to a pin block structure for mounting a large number of contact pins, such as pogo-pins, connected to wires or cables wherein the contact pins can be easily replaced with other pins or changed the positions in the pin block.
BACKGROUND OF THE INVENTION
When testing semiconductor devices, such as packaged integrated circuit (IC or LSI), semiconductor wafers, and the like, a semiconductor test system is usually connected to an automatic handler to automatically test the semiconductor devices. Such a semiconductor test system is sometimes called an LSI tester or an IC tester. Typically, an automatic handler includes a test handler for automatically supplying packaged ICs or LSIs to a test socket of the test system and a wafer prober for automatically positioning a semiconductor wafer relative to a probe card.
Although the present invention is not limited to the application of testing semiconductor wafers and die, but is inclusive of testing and burn-in of packaged semiconductor devices, modules, printed circuit boards and the like. The pin block structure of the present invention can also be used in more general applications including any contact fixtures, multi-pin sockets, and other electrical connectors. However, for the convenience of explanation, the present invention is described mainly with reference to the semiconductor wafer testing.
FIG. 1
shows an example of such a combination of a semiconductor test system and a wafer prober (substrate handler). The semiconductor test system has a test head
100
which is ordinarily in a separate housing and electrically connected to the test system with a bundle of cables
110
. The test head
100
and the substrate handler
400
are mechanically as well as electrically connected with each other. The semiconductor wafers to be tested are automatically provided to a test position of the test head
100
by the substrate handler
400
.
On the test head, the semiconductor wafer to be tested is provided with test signals generated by the semiconductor test system. The resultant output signals from the semiconductor wafer under test (IC circuits formed on the semiconductor wafer) are transmitted to the semiconductor test system. In the semiconductor test system, the output signals are compared with expected data to determine whether the IC circuits on the semiconductor wafer function correctly.
FIG. 2
shows the connection between the test system and the substrate handler in more detail. The test head
100
and the substrate handler
400
are connected through an interface component
140
consisting of a performance board
120
, signal cables
124
such as coaxial cables, a pin block structure including a pogo-pin block
130
and contact pins (pogo-pins)
141
. The test head
100
includes a large number of printed circuit boards
150
which correspond to the number of test channels (pins) of the semiconductor test system. Each of the printed circuit boards
150
has a connector
160
to receive a corresponding contact terminal
121
of the performance board
120
.
The pogo-pin block
130
is mounted on an upper surface of a frame (not shown) of the substrate handler
400
. A large number of pogo-pins
141
are mounted on the pogo-pin block
130
where each of the pogo-pins
141
is connected to the performance board through the cable
124
. As is well known in the art, a pogo-pin is a compressive contact pin having a spring therein. The pogo-pin block
130
is to accurately hold the pogo-pins
141
relative to the substrate handler
400
.
In the substrate handler
400
, a semiconductor device, such as a semiconductor wafer
300
to be tested, is mounted on a chuck
180
. In this example, a probe card
170
is provided above the semiconductor wafer
300
to be tested. The probe card
170
has a large number of probe contactors (such as cantilevers or needles)
190
to contact with contact targets such as circuit terminals or contact pads in the IC circuit of the semiconductor wafer
300
under test.
Contact pads (electrodes) on the upper surface of the probe card
170
are electrically connected to the pogo-pins
141
when the pogo-pin block
130
is pressed against the probe card
170
. Because each pogo-pin
141
is configured to be elastic in the longitudinal direction by the spring therein, it is able to overcome the planarization problem (unevenness of the surface flatness) involved in the probe card, wafer prober frames, or the like. The pogo-pins
141
are also connected to the contact terminals
121
of the performance board
120
through the coaxial cables
124
wherein each contact terminal
121
of the performance board
120
is connected to the printed circuit board
150
of the test head
100
. Further, the printed circuit boards
150
are connected to the semiconductor test system through the cable
110
having several hundreds of inner cables.
Under this arrangement, the probe contactors
190
contact with the surface (contact targets) of the semiconductor wafer
300
on the chuck
180
to apply test signals to the semiconductor wafer
300
and receive the resultant output signals from the wafer
300
. The resultant output signals from the semiconductor wafer
300
under test are compared with the expected data generated by the semiconductor test system to determine whether the IC circuits on the semiconductor wafer
300
functions correctly.
The forgoing is the basic configuration of the connection between the test head of the semiconductor test system and the substrate handler. The configurations of the pin block structure including the pogo-pin block
130
, the pogo-pins
141
fitted in the pogo-pin block, and the probe card
170
for contacting with the pogo-pins are explained in more detail below.
FIG. 3
is a bottom view of the probe card
170
of FIG.
2
. In this example, the probe card
170
has an epoxy ring on which a plurality of probe contactors
190
called needles or cantilevers are mounted. When the chuck
180
mounting the semiconductor wafer
300
thereon moves upward in
FIG. 2
, the tips of the cantilevers
190
contact with the pads or bumps (contact targets) on the wafer
300
. The ends of the cantilevers
190
are connected to transmission lines (not shown) formed in the probe card
170
. The transmission lines are connected to a plurality of electrodes
197
(on the upper surface of the probe card
170
) which further contact with the pogo-pins
141
of FIG.
2
.
FIG. 4
is a cross sectional view of the pin block structure formed of the pogo-pin block
130
having a plurality of pogo-pins therein as shown in FIG.
2
. The pogo-pin block
130
comprises a plurality of pogo-holes
131
, wherein pogo-pins
141
are inserted to be captivated therein. A step like shape is provided to each pogo-hole
131
and pogo-pin
141
so that the inserted pogo-pin
141
is blocked at the predetermined depth in the pogo-hole
131
. The pin block structure further includes a pogo-cap
132
for locking the pogo-pins
141
in the pogo-holes
131
. Thus, the pogo-pins
141
are aligned in the same height on the pogo-pin block
130
without falling down from the pogo-holes
131
.
As noted above, the tips of the pogo-pins
141
contact with the contact receptacles (contact pads)
197
of the probe card
170
when the pogo-pin block
130
is attached to the substrate handler
400
. The other ends of the pogo-pins
141
are connected with the cables
124
such as coaxial cables which are further connected to the contact terminals
121
of the performance board
120
.
In an actual application of the semiconductor device testing, a large number of such pogo-pins, several hundreds for example, must be mounted on the pogo-pin block with a small pitch and high positional accuracy. The pogo-pins
141
captivated by the pogo-holes
131
of the pogo-pin block
130
are arrayed to be accurately provided at predetermined contact positions relative to the

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