Metal fusion bonding – Process – With protecting of work or filler or applying flux
Reexamination Certificate
2001-06-04
2003-04-08
Dunn, Tom (Department: 1725)
Metal fusion bonding
Process
With protecting of work or filler or applying flux
C228S180210, C228S180220
Reexamination Certificate
active
06543676
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
This invention relates generally to organic pin grid array packages. More particularly, the present invention relates to a method of surface mounting the pins for fabricating an organic pin grid array package.
2. Background of the Invention
There are many instances, in which under functional or economic considerations it is desirable to be able to alter the set of electrical components on a circuit board but simultaneously be able to avoid the expense of a board redesign or replacement of an otherwise good circuit board. For example, a computer user may hope to upgrade a computer to include a more powerful and lower voltage-supply microprocessor to replace the old one. However, such changes are often difficult to achieve, because currently a variety of the packaged electrical components are generally soldered to a printed circuit board by means of either the surface mounting technique or through-hole mounting technique.
It has been common to mount a socket or an adaptor on a circuit board, in which the socket or adaptor provides interconnect routing of electrical signals between the electrical components and circuit board. The electrical components prevailingly tend to use pin grid array (PGA) packages and can be plugged into the socket or the adaptor. Consequently, the set of electrical components can be replaced by merely unplugging the old one out of the socket or the adaptor and then plugging a new one into the socket or the adaptor but without the need to further replace the circuit board.
The PGA packages have been used extensively to house integrated circuits, because the array of pins which extend orthogonal from the bottom of the package permits a large number of pins, which is essential for complex circuits with high input-output requirements. The typical prior art PGA-packaged integrated circuit chips are illustrated in
FIGS. 1 and 2
. Referring to
FIG. 1
, a typical cavity down PGA assembly
100
includes a plastic wiring substrate (or say PGA substrate)
101
with a recess cavity
102
and a heat slug or heat spreader
103
bonded to said substrate
101
. A chip
104
is mounted on the heat spreader
103
inside the recess cavity
102
. The conductive wires
105
are used to electrically interconnect the chip
104
with the substrate
101
. After the wire bonding process, the cavity
102
is filled up with an encapsulant
106
to cover and protect the bonding wires
105
and chip
106
against environmental degradation. The external connection pins
107
, by which the substrate
101
will be electrically connected to a socket or an adaptor, are attached to appropriate areas on the top surface
108
of the substrate
101
. As an alternative structure, an additional heat sink may be attached to the backside
109
of the heat spreader
103
if necessary for further enhancing heat dissipation.
Another example of the prior art PGA-packaged integrated circuit chips is shown in
FIG. 2
, in which the packaging assembly
200
includes a chip
201
being mounted on a wiring substrate (or say PGA substrate)
202
by means of the solder balls
203
. The area beneath the chip
201
is covered for protection by an underfill resin
204
which serves as an encapsulant for the sensitive electrical connections (i.e. the solder balls
203
). The external connection pins
205
, by which the chip
201
is electrically connected to a socket or an adaptor, are attached to appropriate areas on the top surface
206
of the chip
201
. In order to further enhance thermal dissipating performance, an additional heat sink may be attached directly to the backside of the substrate
202
. This type of the package is so-called flip chip-pin grid array (FC-PGA) package and has been early proposed by the IBM Corp. in the U.S. Pat. Nos. 3,921,285 (B. Krall) and 4,092,697 (R. N. Spaight).
There are two common existing methods, i.e. through-hole mounting and surface mounting, to attach the pins, such as pins
107
or
205
, onto an organic PGA substrate, as shown in FIG.
3
.
FIG. 3A
shows the so-called pass through-hole mounting method which involves the use of a PGA substrate
301
containing a conductive through hole
302
with plated metal
303
to receive a pin
304
, in which a solder material
305
is used to form the solder joint.
FIG. 3B
illustrates a non-pass through-hole mounting method (i.e. the hole doesn't pass through the substrate
401
), in which a PGA substrate
401
(including conductive layer
401
a
and organic dielectric layer
401
b
) has a conductive via
402
containing a plated metal
403
to receive a pin
404
and a solder material
405
is used to form a solder joint.
FIG. 3C
illustrates a surface mounting method, in which a pad
501
and a layer of solder mask material
502
are made on the surface of an organic substrate
503
. The solder mask layer
502
only partially covers a portion of the pad
501
and leaves an opening
504
to receive a pin
505
. A solder material
506
is used to form a solder joint between the pad
501
and pin
505
.
The major disadvantage with the through-hole technique is that the through hole should be large (e.g. at least larger than 15 mil in diameter) for through-soldering being feasible, which however adversely impacts miniaturization of electronic products. In contrast, for the surface mounting method, the strength of the solder joint is proportional to the height h of the solder joint and the size of the opening
504
, as illustrated in
FIG. 3C
, which is normally much weaker than that of solder joint made by the through-hole technique. However, the surface mounting method is undoubtedly doubt a lower cost manufacturing method compared to the through-hole technique, since the processing step to form the holes for receiving the pins in the wiring substrate could be skipped.
It is therefore desirable to provide a surface mounting method to surface mount the pins onto the PGA substrate, which exhibits the benefits of higher strength of the solder joint, higher reliability, and low manufacturing cost.
SUMMARY OF INVENTION
It is therefore an objective of the present invention to provide a surface mounting method for attaching the pins onto an organic PGA substrate, which is able to result in improved strength and reliability of the solder joint in a PGA package used to electrically interconnect with a socket or an adaptor.
Another objective of this invention is to adopt a method, in which the solder mask layer does not cover any portion of the pad and is configured to allow a solder material to fully fill a well enclosed by the perimeter of the solder mask layer. After pin attachment, the solder material covers and holds firmly the pad.
In summary, a pin attachment method for mounting the pins on a wiring substrate for fabricating a pin grid array package is disclosed. According to the present invention, there is provided an organic wiring board including a surface bearing electrical circuitry which includes at least one contact pad for receiving a pin. A solder mask layer which is placed on the board surface and patterned to expose the pad, and the solder mask layer which does not cover any portion of the pad and forms a well by the perimeter of the solder mask layer around the pad. Subsequently, a pin and a solder material which are placed over the pad in the well. The pin which is then soldered to said pad by a temperature sufficient to melt the solder material.
REFERENCES:
patent: 5313021 (1994-05-01), Sajja et al.
patent: 5400948 (1995-03-01), Sajja et al.
patent: 5982635 (1999-11-01), Menzies et al.
patent: 6194667 (2001-02-01), Jimarez et al.
patent: 6229207 (2001-05-01), Master
patent: 6350136 (2002-02-01), Eckblad et al.
Hsu Shih-Ping
Tung I-Chung
Dunn Tom
Phoenix Precision Technology Corporation
Pittman Zidia
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