Metal fusion bonding – Process – Plural joints
Reexamination Certificate
2000-04-27
2003-06-17
Dunn, Tom (Department: 1725)
Metal fusion bonding
Process
Plural joints
C228S123100
Reexamination Certificate
active
06578754
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates in general to interconnections for semiconductor devices and, in particular, to pillar-shaped connections from a semiconductor chip to a substrate and method for making the connections.
Tin lead based solders is the preferred interconnect material of choice for flip chip bonding of silicon integrated circuits. As dimensions of the electronic devices on the silicon integrated circuits are continually reduced, &agr; particle emissions by lead can cause significant problems. Lead has three stable isotopes which are formed as the end products of natural radioactive decay chains. These stable isotopes, however, usually contain a small amount of residual &agr; particle radioactivity. As the dimensions of electronic devices in silicon integrated circuits become smaller, the distances between the lead-based solder and the devices are also reduced so that the &agr; particle emission from the solder can cause such devices to malfunction.
One way to reduce the effect of &agr; particle emission from solder is to provide a passivation layer covering the electronic devices on silicon. Some materials used for the passivation layer are more effective than others for preserving the integrity of the electronic devices from the &agr; particles. Furthermore, the residual a particle emission from the solder radiate from essentially point sources in the solder, so that the intensity of &agr; particle emission experienced by the electronic devices decreases rapidly with the distances separating the devices from the solder. Shown below is a table setting forth five different materials serving as the medium separating electronic devices from the solder.
Effective
MEDIA
Density
Mol. Wt.
-dE/dx
Thickness
(Compound)
&rgr; (g.cm
−3
)
M(g)
(eV.cm
2
/1e15 atoms)
d(cm)
Air
1.161e-03
39.11
20.96
10.83
Polyimide
1.61
38.0
18.91
0.0084
Epoxy
1.20
40.0
19.68
0.0114
SiO
2
2.65
60.0
27.42
0.0055
Si
3
N
4
3.17
140.0
28.18
0.0105
As can be seen from the table above, if air is the only medium that separates the electronic devices from the solder, then in order for the electronic devices not be significantly affected by the &agr; particle emission from the solder, the effective thickness of the air medium separating the electronic devices and the solder should be at least 10.83 cm, which is unacceptable for most applications. From the above table, it will be noted that the best barrier layer substance in terms of minimum absorption length for absorption of &agr; particles from the solder is silicon dioxide, followed by polyimide. Where silicon dioxide or another solid material is used as the passivation layer, only part of the medium separating the electronic devices from the solder is occupied by the material, with the remaining part occupied by air or another material not as effective in absorbing &agr; particles. It will be noted from the table, however, that even where silicon dioxide is used as a compound for the passivation layer covering the electronic devices on silicon, it is preferable that the electronic devices and the solder be separated by at least 0.0055 cm or 55 microns. For polyimide passivation layers, the separation is preferably at least 84 microns.
In conventional interconnect systems, lead-based solders are used for connecting flip chips to substrates. Aside from the &agr; particle emission problem described above, as the structural dimensions of electronic devices get smaller, the use of lead-based solder bumps is disadvantageous also because it may be difficult to achieve a fine pitch between adjacent interconnects without bridging which causes electrical shorting. When the solder bump is formed by electroplating, the bump size in the horizontal plane of a 100 micron high solder ball will be around 120 microns, and the solder bump is in the shape of a mushroom. Therefore, if the pitch or distance between adjacent interconnects using solder bumps of such height is reduced to below 150 microns in either the array or peripheral format, bump ridging can easily occur. It is, therefore, desirable to provide an improved interconnect system to achieve finer pitch with minimum probability of bump bridging and where &agr; particle emission will not significantly affect the functions of electronic devices on the semiconductor chips.
In the document entitled “Wire Interconnect Technology, A New High-Reliability Tight-Pitch Interconnect Technology,” by Love et al., from Fujitsu Computer Packaging Technologies, Inc. an all copper interconnect post is proposed. Instead of using lead based solder, the flip chip is connected to a substrate by means of an all copper post which is about 45 or 50 microns in length. While such copper-based interconnects may be able to achieve a finer pitch between adjacent interconnects, such proposed solution still does not avoid the problem of the &agr; particle emission described above. As shown in
FIG. 1
of the article by Love et al., solder is used to attach the copper posts to the substrate. Since the height of the copper post or pillars is not more than 50 microns in height, even where silicon dioxide is used as the passivation layer covering the electronic devices on the flip chips, the electronic devices may still be adversely affected by &agr; particle emission by the solder used to attach the copper posts to the substrate. Furthermore, as known to those skilled in the art, the space between the semiconductor flip chip and the substrate is usually filled with an underfill material to provide support and stability to the interconnect structure. Typically, the process of providing the underfill material is by injection that requires a certain minimum separation between the semiconductor chip and the substrate. For most injection processes, the minimum separation is about 75 microns. Therefore, using the interconnect structure proposed by Love et al. in the article, there appears to be inadequate separation between the semiconductor chip and the substrate for injecting the underfill material. The process employed by Love et. al appears to limit the height of the copper post achievable to not more than 50 microns.
None of the above-described interconnect systems is entirely satisfactory. It is, therefore, desirable to provide an improved interconnect system in which the above-described difficulties are not present.
SUMMARY OF THE INVENTION
This invention is based on the observation that an elongated pillar may be advantageously used for connecting a semiconductor chip to a substrate, where the pillar comprises two elongated portions, one portion including copper and another portion including solder. The portion including copper is in contact with the semiconductor chip and has a length not less than about 50 microns. Preferably, the total length of the pillar is not less than about 55 microns. In a more preferred embodiment, the length of the pillar is not less than about 85 microns, with the length of the portion of the pillar including copper not less than about 55 microns.
Using the elongated pillar of this invention, the separation between the solder in the pillar or any other solder used in the interconnect on the one hand and electronic devices on the semiconductor chip on the other hand can be made to exceed 55 microns or even 84 microns so that the electronic devices on the semiconductor chip will not be adversely effected by &agr; particle emission from the solder when silicon dioxide or polyimide is used as the passivation layer. Where the length of the pillar exceeds 75 microns, adequate separation is provided between the semiconductor chip and the substrate for the injection of the underfill material. Furthermore, by providing elongated pillars of adequate length and suitable cross-sectional dimensions connecting the semiconductor chip to the substrate, the stress induced in the connection between the semiconductor chip and the pillar due to warpage is much reduced, which also reduces the chances of chip failure caused by shear stress on account of the warpage.
The elongated pillar may be formed by first
Ackerman Stephen B.
Advanpack Solutions Pte. Ltd.
Dunn Tom
Johnson Jonathan
Saile George O.
LandOfFree
Pillar connections for semiconductor chips and method of... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Pillar connections for semiconductor chips and method of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Pillar connections for semiconductor chips and method of... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3114707