Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2007-02-06
2007-02-06
Tran, Henry N. (Department: 2629)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C310S324000, C310S328000, C310S366000
Reexamination Certificate
active
10805521
ABSTRACT:
A first electrode layer12, a first piezoelectric film layer13, a second electrode layer14, a second piezoelectric film layer15, and a third electrode layer16are layered in that order on a substrate11; these are constrained so as pot to expand or contract in a thickness direction and a piezoelectric transducer is constructed thereby. A plurality of gate lines201and202, a plurality of data lines203and204intersecting with the gate lines, and thin film transistors205and207, disposed at the intersections of the abovementioned gate lines and data lines, are established; one source-drain of the abovementioned thin film transistors is connected to the abovementioned data lines; another source-drain of the abovementioned thin film transistors is connected to the input sides of the abovementioned thin film piezoelectric transducers208through210; the output sides of the abovementioned thin film piezoelectric transducers are connected to the electrodes of electrophoretic ink display elements; and an electrophoretic ink display apparatus is constructed thereby.
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Hasegawa Kazumasa
Shimoda Tatsuya
Harness & Dickey & Pierce P.L.C.
Seiko Epson Corporation
Tran Henry N.
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