Electricity: measuring and testing – Impedance – admittance or other quantities representative of... – Calibration
Reexamination Certificate
2002-01-30
2004-11-16
Lamarre, Guy J. (Department: 2133)
Electricity: measuring and testing
Impedance, admittance or other quantities representative of...
Calibration
C368S120000
Reexamination Certificate
active
06819117
ABSTRACT:
BACKGROUND
1. Field of the Invention
The present invention relates to timing measurement of signals in PICA (picosecond imaging circuit analysis) systems, and particularly to methods and apparatus for timing measurement and calibration of timing measurement.
2. Prior Art
New package types, shrinking process geometries and new material pose challenges for gathering vital timing measurement during the integrated circuit (IC) design debug and validation process. Increasingly sensitive devices are easily perturbed during probing, which skews results and slows the design process.
Fault localization methods using beam probe systems are time-consuming even with access to IC layout knowledge since each node must be probed serially to trace the location of a faulty circuit element. Tester and other equipment time is often limited, forcing design debug experts to extract timing measurements from the device one probing session at a time, often adding weeks to the debug and verification cycle.
Timing data acquisition and analysis can be a development bottleneck. With conventional serial probe systems, skilled IC diagnostic experts are required to analyze the critical device data to know which node to probe next. Though companies often develop multiple products simultaneously, data acquisition, review and analysis capabilities are available only at the probe system's site. If a single node is missed, a new probe session must be set up, effectively limiting progress to one device at a time.
Silicon on insulator (SOI) technology offers increased power capabilities and device performance, but its sensitive structure requires non-invasive probing. Devices manufactured with 0.13-micron geometry have critical signal nodes so small and numerous that the acquisition process is too time-consuming for efficient probe by serial, beam-based instruments.
Picosecond Imaging Circuit Analysis (PICA) technology developed by IBM uses naturally occurring light emission from stimulated CMOS transistors to extract timing measurements and localize faults. Detecting the emitted light with high-speed optical detectors allows circuit switching to be monitored. By imaging and time-resolving light emission from many devices on an operating chip, the flow of information through the chip can be displayed as a movie.
More details of PICA methods and systems are found in the following documents which are incorporated herein by this reference: U.S. Pat. No. 5,940,545 dated Aug. 17, 1999, Kash et al.,
Noninvasive Optical Method for Measuring Internal Switching and Other Dynamic Parameters of CMOS Circuits
; U.S. Pat. No. 6,028,952 dated Feb. 22, 2000, Kash et al.,
System and Method for Compressing and Analyzing Time
-
Resolved Optical Data Obtained from Operating Integrated Circuits
; U.S. Pat. No. 6,172,512 dated Jan. 9, 2001, Evans et al.,
Image Processing Methods for the Optical Detection of Dynamic Errors in Integrated Circuits
; U.S. Pat. No. 6,304,668 (withdrawn) dated Oct. 16, 2001, Evans et al.,
Using Time Resolved Light Emission from VLSI Circuit Devices for Navigation on Complex Systems
; European patent publication EP 0 937 989 published Aug. 28, 1999, Evans et al., IBM,
Using Time Resolved Light Emission from VLSI Circuit Devices for Navigation on Complex Systems
; J. BUDE,
Hot
-
carrier luminescence in Si
, PHYS. REV. B, 45(11), Mar. 15, 1992, pages 5848-5856; S. VILLA et al.,
Photon emission from hot electrons in silicon
, PHYS. REV. B, 52(15), Oct. 15, 1995-I, pages 10993-10999; J. KASH et al.,
Full Chip Optical Imaging of Logic State Evolution in CMOS Circuits
, IEDM 96 Late News Paper (1996) 1, pages 934-936; D. KNEBEL et al.,
Diagnosis and Characterization of Timing
-
Related Defects by Time
-
Dependent Light Emission
, ITC PROCEEDINGS 1998; M. BRUCE et al.,
Waveform Acquisition from the Backside of Silicon Using Electro
-
Optic Probing
, PROCEEDINGS FROM THE 25
TH
INTERNATIONAL SYMPOSIUM FOR TESTING AND FAILURE ANALYSIS, Nov. 14-18, 1999, pages 19-25; T. EILES et al.,
Optical Probing of VLSI IC's from the Silicon Backside, Proceedings from the
25
th
International Symposium for Testing and Failure
Analysis, Nov. 14-18, 1999, pages 27-33, and M. MCMANUS,
Picosecond Imaging Circuit Analysis of the IBM G
6
Microprocessor Cache
, PROCEEDINGS FROM THE 25
TH
INTERNATIONAL SYMPOSIUM FOR TESTING AND fAILURE ANALYSIS, Nov. 14-18, 1999, pages 35-38.
Precise time resolution of the detected photons is important in electro-optic probing. Suitable high-resolution timing measurement methods and apparatus are desired, along with methods for their calibration.
SUMMARY OF THE INVENTION
In accordance with embodiments of the invention, methods are provided for calibrating a timer having a coarse measurement capability in which time intervals defined by boundaries are counted and a fine measurement capability in which time between boundaries is interpolated using a voltage ramp, comprising: determining alignment of the voltage ramp relative to a reference-clock signal having a known relationship to the boundaries; sampling the voltage ramp at a plurality of known times relative to the boundaries; and determining slope of the voltage ramp as a function of time from the voltage samples.
The voltage ramp can be aligned relative to the time interval boundaries. The time intervals can be defined by an interval clock signal at a first frequency, and the interval clock signal phase-locked to a reference-clock signal at a second frequency to define phase relationship between the interval-clock signal and the reference-clock signal. Aligning the voltage ramp comprises starting the voltage ramp at a defined number of periods of the reference-clock signal following coincidence of the interval-clock signal and the reference-clock signal. Sampling the voltage ramp at a plurality of known times comprises: starting the voltage ramp following a first number of cycles of the reference-clock signal following coincidence of the interval-clock signal and the reference-clock signal, and sampling the voltage ramp at a subsequent clock edge of the interval-clock signal to obtain a first voltage sample.
Sampling the voltage ramp at a plurality of known times can comprises: starting the voltage ramp following a second number of cycles of the reference-clock signal following coincidence of the interval-clock signal and the reference-clock signal; and sampling the voltage ramp at a subsequent clock edge of the interval-clock signal to obtain a second voltage sample. Preferably the interval-clock signal and the reference-clock signal are substantially out of phase with one another when voltage ramp is sampled.
The methods can further comprise determining from the phase relationship between the interval-clock signal and the reference-clock signal a time difference between the respective known times at which the voltage ramp is sampled to obtain the first voltage sample and the second voltage sample. Determining slope of the voltage ramp may comprise calculating the a ratio of difference in voltage between the second voltage sample and the first voltage sample to the time difference between the respective known times at which the voltage ramp is sampled to obtain the first voltage sample and the second voltage sample.
Embodiments of apparatus in accordance with the invention include an event timer and comprise: a coarse-measurement counter for counting time intervals defined by boundaries, a fine-measurement interpolator employing a voltage ramp to measure a time delay of less than one of the time intervals; a source of an interval-clock signal at a first frequency and a reference-clock signal at a second frequency with a defined phase relationship between the interval-clock signal and the reference-clock signal; and an analog-to-digital converter for sampling the voltage ramp at a plurality of known times relative to the boundaries to obtain voltage samples from which slope of the voltage ramp can be calculated.
The apparatus may further comprise a processor for determining slope of the voltage ramp as a function of time fro
Credence Systems Corporation
Kerveros James C.
Lamarre Guy J.
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