Semiconductor device manufacturing: process – Including control responsive to sensed condition
Reexamination Certificate
2005-12-21
2008-07-22
Clark, Jasmine J (Department: 2815)
Semiconductor device manufacturing: process
Including control responsive to sensed condition
C257S700000, C257S723000, C257S777000, C257SE23169, C257SE23174, C257SE23178, C257S665000, C029S709000, C029S712000, C029S740000
Reexamination Certificate
active
07402442
ABSTRACT:
A physically secure processing assembly is provided that includes dies mounted on a substrate so as to sandwich the electrical contacts of the dies between the dies and the substrate. The substrate is provided with substrate contacts and conductive pathways that are electrically coupled to the die contacts and extend through the substrate. Electrical conductors surround the conductive pathways. A monitoring circuit detects a break in continuity of one or more of the electrical conductors, and preferably renders the assembly inoperable. Preferably, an epoxy encapsulation is provided to prevent probing tools from being able to reach the die or substrate contacts.
REFERENCES:
patent: 4407007 (1983-09-01), Desai et al.
patent: 4764804 (1988-08-01), Sahara et al.
patent: 4994735 (1991-02-01), Leedy
patent: 5010389 (1991-04-01), Gansauge et al.
patent: 5110664 (1992-05-01), Nakanishi et al.
patent: 5306866 (1994-04-01), Gruber et al.
patent: 5424573 (1995-06-01), Kato et al.
patent: 5608262 (1997-03-01), Degani et al.
patent: 5717229 (1998-02-01), Zhu
patent: 5804004 (1998-09-01), Tuckerman et al.
patent: 5953213 (1999-09-01), Napierala
patent: 6026221 (2000-02-01), Ellison et al.
patent: 6150124 (2000-11-01), Riedel
patent: 6268660 (2001-07-01), Dhong et al.
patent: 6301121 (2001-10-01), Lin
patent: 6369444 (2002-04-01), Degani et al.
patent: 6500699 (2002-12-01), Birdsley et al.
patent: 6579743 (2003-06-01), Clevenger et al.
patent: 6620647 (2003-09-01), Kroner
patent: 6844631 (2005-01-01), Yong et al.
patent: 6861858 (2005-03-01), Chen et al.
patent: 6992896 (2006-01-01), Fraley et al.
patent: 7105933 (2006-09-01), Haza et al.
patent: 2003/0015709 (2003-01-01), Emrick et al.
patent: 2004/0075170 (2004-04-01), Degani et al.
patent: 095900 (1999-11-01), None
patent: 05-090559 (1991-09-01), None
patent: 6045514 (1994-02-01), None
patent: 11345932 (1999-11-01), None
patent: 11067919 (2001-07-01), None
Spielberger, R.K., et al., “Silicon-on-Silicon Packaging,” IEEE Transactions on Components, Hybrids, and Manufacturing Technology, vol. 7, Issue 2, pp. 193-196, Jun. 1984.
Ketchan, M.B., “High-Level Discretionary Wiring for Wafer Scale Integration,” IBM Technical Disclosure Bulletin, vol. 30, No. 5, Oct. 1987.
Stephansen, S., et al., “Low Cost, High Performance Silicon-on-Silicon Multichip Modules,” Wescon/90, Conference Record, Nov. 13-15, 1990, Anaheim, California.
Frye, Robert C., et al., “Silicon-on-Silicon MCMs with Integrated Passive Components,” IEEE Multi-Chip Module Conference, Santa Cruz, California, Mar. 18-20, 1992, MCMC-92 Proceedings, pp. 155-158.
Day, Ray-Long, et al., “A Silicon-on-Silicon Multichip Module Technology with Integrated Bipolar Components in the Substrate,” IEEE Multi-Chip Module Conference, Santa Cruz, CA., Mar. 15-17, 1994, MCMC-94 Proceedings, pp. 64-67.
Contreras, J.L., Silicon Substrate Multichip Modules for Innovative Products (SUMMIT)—Developments in an EC Funded Project, EuPac '98: European Conference on Electronic Packaging Technology, 3rd, and International Conference on Interconnection Technology in Electronics, 9th, Nuremberg, Jun. 15-17, 1998, Lectures and Poster Show Contributions, pp. 122-126.
Degani, Y., et al., “A Novel MCM Package for RF Applications,” IEEE/CPMT International Electronics Manufacturing Technology Symposium, 23rd, Austin, Oct. 19-21, 1998, Proceedings, pp. 225-231.
Kanbach, H., et al., “3D Si-on-Si Stack Package,” International Conference on High Density Packaging and MCMs, Denver, Apr. 6-9, 1999 (Proceedings of SPIE, vol. 3830), pp. 248-253.
Barton, J., et al., “Reliability Evaluation of a Silicon-on-Silicon MCM-D Package,” ISSN 0026-2714, vol. 41, No. 6, pp. 779-932, Jun. 2001.
Condorelli Vincenzo
Feger Claudius
Gotze Kevin C.
Hadzic Nihad
Knickerbocker John U.
Bongini Stephen
Clark Jasmine J
Cutter Lawrence D.
Fleit Kain Gibbons Gutman Bongini & Bianco P.L.
LandOfFree
Physically highly secure multi-chip assembly does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Physically highly secure multi-chip assembly, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Physically highly secure multi-chip assembly will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3964382