Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
2002-02-05
2003-11-11
Powell, William A. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C216S038000, C216S088000, C438S740000, C438S745000
Reexamination Certificate
active
06645864
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
This invention relates to methods of forming a via hole within a trench in a layer of low dielectric constant dielectric which prevents via hole poisoning caused by removal of the resist mask used in etching the trench.
(2) Description of the Related Art
Resist scum can form under certain conditions and remain after a resist mask is stripped. This resist scum can form a barrier between conducting materials, such as conducting material in a via hole and a conducting electrode, causing via poisoning.
U.S. Pat. No. 5,932,487 to Lou et al. describes a method of forming a planar intermetal dielectric over conductive metal structures. A liner oxide layer is used over the conductive metal structures.
U.S. Pat. No. 5,643,407 to Chang describes the use of a nitrogen plasma treatment of a layer of spin-on-glass after via hole etching to avoid via poisoning.
U.S. Pat. No. 6,060,384 to Chen et al. describes the use of spin on HSQ, hydrogen silsesquioxane, to gap fill metal layers in high density multi-layer devices. The degradation of the HSQ layer due to photoresist stripping is overcome by treating the degraded layer with a hydrogen containing plasma.
U.S. Pat. No. 6,100,179 to Tran describes the use of a conformal dielectric liner encapsulating metal features before depositing a HSQ, hydrogen silsesquioxane, gap fill layer to form an electromigration resistant structure.
U.S. Pat. No. 6,093,635 to Tran et al. describes heat treating a HSQ, hydrogen silsesquioxane, gap fill layer in an inert atmosphere before filling via holes to thoroughly outgas water absorbed during solvent cleaning of the via hole.
U.S. Pat. No. 6,074,941 to Hsieh et al. describes a plasma treatment of a spin-on-glass layer after forming unlanded vias. The plasma comprises hydrogen and another gas.
SUMMARY OF THE INVENTION
In the fabrication of semiconductor integrated circuit devices it is often desirable to use dielectric materials having a low dielectric constant, hereinafter referred to as low k dielectric materials. Frequently trenches and via holes are formed in the low k dielectric wherein the via hole lies within the trench. The via holes are etched through the layer of low k dielectric material to expose metal contacts under the layer of low k dielectric material, using an appropriate etching method and a first resist pattern. After the via hole has been formed the first resist pattern is stripped and a trench for conducting material is formed in the layer of low k dielectric material using a second resist pattern. The trench passes directly over the via hole. An amine radical, NH
x
, released from the low k dielectric material, especially after damage during the via etching, can interact with the second resist, used. to form the trench in the layer of low k dielectric material, and form resist scum on the top of the via. This problem is known as resist poisoning of the via.
It is a principle objective of at least one embodiment of this invention to provide a method of forming a trench and via hole in a layer of low k dielectric formed on a substrate which avoids the problem of resist poisoning of the via.
It is another principle objective of at least one embodiment of this invention to provide a method of forming a trench and a via hole in a layer of low k dielectric formed on a substrate, having a layer of dielectric etch stop or metal diffusion barrier formed thereon, which avoids the problem of resist poisoning of the via.
These objectives are achieved by first forming a layer of low k dielectric, such as porous silicon dioxide, black diamond (methyl doped porous silicon dioxide), or the like on a semiconductor substrate having a conducting electrode or contact formed therein. A layer of dielectric etch stop or metal diffusion barrier can be formed on the substrate. A via hole is then formed in the layer of low k dielectric using a first resist pattern, thereby exposing part of the conducting electrode or contact. A layer of amorphous silicon is then deposited on the layer of low k dielectric using physical vapor deposition or sputtering thereby forming a layer of amorphous silicon on the top of the layer of low k dielectric, the sidewalls of the via hole, and the exposed conducting electrode or contact at the bottom of the via hole.
A layer of second resist is then formed on the substrate, filling the via hole with second resist. The layer of second resist is then patterned to form a trench pattern, thereby removing the second resist in that part of the via above a first plane and leaving the second resist in that part of the via below the first plane. The first plane is a first distance below the top surface of the layer of low k dielectric. A trench is then etched in the layer of low k dielectric. The trench extends to the level of the first plane. The resist is then stripped and a layer of barrier metal can be deposited.
A layer of conducting material, such as copper, is then deposited on the layer of barrier metal filling the trench and the via hole. That part of the layer of conducting material, that part of the layer of barrier metal, and that part of the layer of amorphous silicon above the top surface of the layer of dielectric are then removed, using a method such as chemical mechanical polishing. The thermal cycling seen by the substrate converts the amorphous silicon and the barrier metal below the first plane to metallic silicon nitride. The amorphous silicon prevents via poisoning during the developing and removal of the second resist.
REFERENCES:
patent: 5643407 (1997-07-01), Chang
patent: 5932487 (1999-08-01), Lou et al.
patent: 6060384 (2000-05-01), Chen et al.
patent: 6074941 (2000-06-01), Hsieh et al.
patent: 6093635 (2000-07-01), Tran et al.
patent: 6100179 (2000-08-01), Tran
Li Lain Jong
Lin Cheng Chung
Ackerman Stephen B.
Powell William A.
Prescott Larry J
Taiwan Semiconductor Manufacturing Company
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