Boots – shoes – and leggings
Patent
1995-09-08
1997-12-16
Teska, Kevin J.
Boots, shoes, and leggings
364488, G06F 1750
Patent
active
056992653
ABSTRACT:
A process for designing an integrated circuit chip includes specifying a set of cells, a set of wiring nets for interconnecting the cells, and a set of regions on the chip in which the cells are to be placed. An assignment of the cells of the set to the regions is generated, and the set of cells is randomly divided into a first subset of cells which remain in the assignment, and a second subset of cells which are removed from the assignment. Penalties are computed for assigning the cells of the second subset to the regions respectively, and the cells of the second subset are assigned to the regions such that a total penalty thereof is minimized. The process is repeated iteratively with the size of the second subset being progressively reduced relative to the size of the first subset until an end criterion is reached.
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Aleshin Stanislav V.
Andreev Alexander E.
Koford James S.
Kudryavtsev Valeriy B.
Podkolzin Alexander S.
Garbowski Leigh Marie
LSI Logic Corporation
Teska Kevin J.
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