Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2002-03-19
2004-06-01
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S462000, C438S737000, C438S906000
Reexamination Certificate
active
06743735
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to photoresist removal from alignment marks in semiconductor processing, and more specifically to such removal through wafer edge exposure.
BACKGROUND OF THE INVENTION
Deposition and patterning are two of the basic steps performed in semiconductor processing. Patterning is also referred to as photolithography, masking, oxide or metal removal, and microlithography. Patterning enables the selective removal of material deposited on a semiconductor substrate, or wafer, as a result of deposition. For example, as shown in
FIG. 1A
, a layer
104
has been deposited on a substrate
102
. After the photolithography process is performed, as shown in
FIG. 1B
, some parts of the layer
104
have been selectively removed, such that gaps
106
a
and
106
b
are present within the layer
104
. A photomask, or pattern, is used (not shown in
FIG. 1B
) so that only the material from the gaps
106
a
and
106
b
are removed, and not the other portions of the layer
104
. The process of adding layers and removing selective parts of them, in conjunction with other processes, permits the fabrication of semiconductor devices.
Alignment is critical in photolithography and deposition, as well as in other semiconductor processes. If layers are not deposited properly, or if they are not selectively removed properly, the resulting semiconductor devices may not function, relegating them to scrap, which can be costly. Therefore, alignment marks are placed on the semiconductor wafer for the proper positioning during the deposition and photolithography processes. This is shown in
FIG. 2
, where the semiconductor wafer
202
has alignment marks, such as the alignment square
204
, thereon. When the photomask
206
is positioned over the wafer
202
, its own alignment marks, such as the alignment square
208
, is aligned with the alignment marks of the wafer
202
. For example, the alignment square
208
of the photomask
206
is aligned so that the alignment square
204
of the wafer
202
is centered therein.
Alignment is especially critical where more a number of metal or other layers have already been deposited on the wafer. Subsequent deposition of silicon dioxide or other layers in such instances usually requires that the alignment marks on the wafer be exposed for proper overlay of the silicon dioxide or other layers. While a mask may prevent the layers themselves from obfuscating the alignment marks, the photoresist used to pattern or perform other processing of these layers cannot be masked, and covers or at least blurs the alignment marks. Without clear exposure of the alignment marks, however, overlay misalignment can result. Overlay misalignment is also referred to as overlay registration error. Misalignment is a serious problem, and can result in significant semiconductor wafer scrap. Wafer scrap can sometimes be reused, but often is discarded, resulting in added costs incurred by the semiconductor foundry.
The conventional approach to exposing photoresist-obfuscated alignment marks on the wafer after a number of layers have been deposited on the wafer is to use a photolithographic clear out process. This process is also referred to as the clear out window process. A general description of the effects of the clear out process is described with reference to
FIGS. 3A and 3B
. As shown in
FIG. 3A
, the alignment marks
304
are hidden from view by the photoresist
302
that have been deposited on the silicon wafer, and are indicated as such as dotted. To maintain the alignment marks
304
, a photolithographic clear out process is performed, which clears the photoresist
302
from around the alignment marks
304
. The results of the clear out process are shown in
FIG. 3B
, where a window
306
has been created around the alignment marks
304
, exposing the underlying silicon wafer.
FIGS. 4A and 4B
show how the clear out process can generally be performed. In
FIG. 4A
, a mask
402
is shown that contains an auxiliary pattern
402
. The mask
402
can also be a reticle. The auxiliary pattern
402
contains no device circuitry, and surrounds a smaller pattern
405
in order to clear out a specified window area and isolate the smaller pattern
405
. In this case, the auxiliary pattern
402
would correspond to the alignment marks
304
of
FIG. 3B
, such that a part of the photoresist
302
remains surrounded by the alignment marks
304
as shown in FIG.
3
B. By comparison, in
FIG. 4B
, a mask
406
is shown that contains a blank pattern
408
, where the mask
406
may also be a reticle. The blank pattern
408
contains no circuitry, and clears out a specified window area, such that no part of the resist
302
of
FIG. 3B
would remain surrounded by the alignment marks
304
if the blank pattern
408
were used in lieu of the auxiliary pattern
402
of FIG.
4
A.
A more specific manner by which alignment marks are exposed using a conventional clear out process is shown by reference to FIG.
5
. The wafer
502
has a number of deposition layers, such that the surface of the wafer
502
, with its alignment marks thereon, is not visible. Specifically, the alignment marks are obfuscated or blurred by the photoresist that was applied during patterning or other processing of the deposition layers. Two alignment mark areas are exposed, a lower-left area
504
, and an upper-right area
506
. The alignment mark areas
504
and
506
are not drawn to scale, but rather are much larger than what is typical for purposes of illustrative clarity. Four clear-out windows are used to expose each of the areas
504
and
506
. The clear-out windows
508
a
,
508
b
,
508
c
, and
508
d
expose the alignment marks within the area
504
, whereas the clear-out windows
510
a
,
510
b
,
510
c
, and
510
d
expose the alignment marks within the area
506
.
Employing a clear out window process to expose alignment marks so that subsequent silicon dioxide or other layers can be deposited without overlay registration error is, however, a time-consuming, and therefore costly, process. As demonstrated in conjunction with
FIG. 5
, at least eight exposure images may have to be taken to expose the alignment marks within just two alignment mark areas. Performing each particular clear out process generally takes at least two seconds, usually due to the time involved to change the reticle or mask size. This means that exposing the alignment marks requires at least eight seconds per silicon wafer, which can be an intolerable and costly delay in semiconductor manufacture. Further, exposure of the alignment marks within the alignment mark areas effectively reduces the usage area of the reticle or the mask.
Therefore, there is a need for exposing alignment marks within alignment mark areas without employing a conventional photolithographic clear out process. There is a need for such exposure without adding significant time and cost to the semiconductor manufacture process. Such exposure should desirably not reduce the effective usage area of the reticle or the mask. For these and other reasons, there is a need for the present invention.
SUMMARY OF THE INVENTION
The invention relates to removing photoresist from alignment marks on a semiconductor wafer through a wafer edge exposure process. The alignment marks on the wafer are covered by photoresist resulting from processing of one or more layers that have been deposited on the semiconductor wafer. To reveal the alignment marks, one or more parts of the edge of the wafer are exposed, removing the photoresist from these parts. The exposure of the one or more parts of the wafer is accomplished without performing a photolithographic clear out process. Rather, a wafer edge exposure (WEE) process is inventively utilized, as this process is designed to clean the edge of the wafer for optimized cleanliness of subsequent processes. Once the WEE process is performed, subsequent layers may be deposited by aligning them using the revealed alignment marks.
The invention provides for advantages over the prior art. Significantly, the WEE pro
Chen Chung-Jen
Chen Hsin-Yuan
Chu Po-Tao
Wu Cheng-Ming
Yang Tai-Ming
Elms Richard
Taiwan Semiconductor Manufacturing Co. Ltd
Tung & Associates
Wilson Christian D.
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