Photolithography alignment mark and manufacturing method

Details Photolithography alignment mark and manufacturing method Photolithography alignment mark and manufacturing method

1997-04-21

1998-07-21

Powell, William

Semiconductor device manufacturing: process

Chemical etching

Combined with the removal of material by nonchemical means

216 38, 216 39, 257752, 257797, 438633, 438697, 438724, H01L 2100

Patent

active

057834903

ABSTRACT:
An alignment mark and method of forming an alignment mark are described wherein the alignment mark is formed in an alignment hole formed in a second, or inter-metal, dielectric layer and extends a step height above the second dielectric layer. The second dielectric layer is formed over a first, or inter-level, dielectric layer. The alignment mark is formed using a third, or dummy, dielectric layer formed on a planarized second dielectric layer. An alignment mark hole is formed in the second and third dielectric layers. A layer of conductor metal is formed over the third dielectric layer filling the alignment hole. That part of the conductor metal above the plane of the third dielectric layer is removed. The third dielectric layer is then removed leaving an alignment mark extending above the second dielectric layer by a step height.

REFERENCES:
patent: 4632724 (1986-12-01), Chesebro et al.
patent: 5234868 (1993-08-01), Cote
patent: 5401691 (1995-03-01), Caldwell
patent: 5482893 (1996-01-01), Okabe et al.
patent: 5503962 (1996-04-01), Caldwell
patent: 5622899 (1997-04-01), Chao et al.
patent: 5627110 (1997-05-01), Lee et al.

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