Photolithographic technique of emitter tip exposure in FEDS

Details Photolithographic technique of emitter tip exposure in FEDS Photolithographic technique of emitter tip exposure in FEDS

1996-02-07

1999-01-12

Ramsey, Kenneth J.

Electric lamp or space discharge component or device manufacturi

Process

With assembly or disassembly

H01J 902

Patent

active

058578846

ABSTRACT:
Aligned gate structures for field emitter display devices are formed by overlaying a substrate, having at least one emitter tip thereon, successively with an insulating layer, a conductive layer, and a photoresist layer. The photoresist layer is then exposed to create fixed and unfixed regions. The unfixed regions are developed and etched to remove the conductive layer under the unfixed regions. The insulating layer is then etched to expose the emitter tips and the photoresist layer removed.

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Busta, Heinz H., Review Vacuum microelectronics-1992, J. Micromech. Microeng. 2 (1992) 43-74.

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