Semiconductor device manufacturing: process – Making device or circuit emissive of nonelectrical signal – Having diverse electrical device
Reexamination Certificate
1999-03-05
2004-11-09
Zarabian, Amir (Department: 2822)
Semiconductor device manufacturing: process
Making device or circuit emissive of nonelectrical signal
Having diverse electrical device
C438S026000, C438S029000, C438S116000, C257S059000, C257S072000, C349S155000, C349S156000
Reexamination Certificate
active
06815239
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
This invention relates to new methods of photolithographic fabrication of alignment posts and optical interference layers directly on liquid-crystal-on-silicon displays.
(2) Description of the Prior Art
The picture quality of liquid crystal displays that are created using as simple a design as seven segments to complex designs using millions of pixels is determined by the structure that is used to control the variation of the height of the pixels and the location of the external wires after wafer processing has been completed. There are known processes for creating insulating alignment posts based on preformed glass micro-spheres and rods; relatively low series resistance posts can be obtained by means of selective deposition of polysilicon and metallic silicide. (The making of metallic vias and contacts is a comparatively well known processing art.)
U.S. Pat. No. 5,498,925 to Bell et al describes the formation of posts in flat panel displays using processes based on a heat-treated slurry or paste upon a glass plate. U.S. Pat. No. 5,597,736 teaches the function of a light-blocking layer deposited upon a semiconductor substrate material that can emit light. U.S. Pat. Nos. 5,744,824 and 5,748,828 show various LCD structures and external optics.
Until now, it has been difficult to construct alignment posts using photolithography and also add optical interference layers simultaneously onto a semiconductor substrate material used to control the gray-level of each pixel.
BRIEF SUMMARY OF THE INVENTION
A principal object of the present invention is to describe various new methods for building a flat-panel liquid-crystal display upon an integrated circuit (IC) die with inter-related alignment between the posts supporting the overlaying glass cover plate and optical interference layers employed to improve image quality.
Another object of this invention is to describe effective and very manufacturable methods of photolithographic formation of insulating alignment posts (also called studs or pillars). These methods can be used in processing many different device types, and are described in this application for liquid crystal display devices as a way of illustrating their embodiment at a pixel density beyond that achievable with preformed micro-glass spheres and rods.
A further object of the present invention is to describe methods of deposition for both the posts and the optical interference layers that are independent of each other and retain their desired feature during deposition of subsequent features. The various methods are classified into five method categories: 1) silicon oxide wet etching; 2) amorphous silicon plasma etching; and 3) nitride plug filling; 4) insulating material lift-off; 5) photosensitive polyimides.
Five new methods for the formation of an improved liquid-crystal-on-silicon display are described, in which the device structure is enhanced by the photolithographic building of alignment posts among the mirror pixels of the micro-display. At the same time these five methods accommodate the fabrication of an optical interference multilayer that improves the image quality of the reflected light. These five methods are:
Silicon Dioxide Posts by Wet Etching—wherein said alignment posts are formed by the process of silicon dioxide wet etching upon the said silicon substrate.
Amorphous Silicon Posts by Plasma Etching—wherein said alignment posts are formed by the process of amorphous silicon plasma etching upon the said silicon substrate.
Silicon Nitride Posts by Plug Filling—wherein said alignment posts are formed by the process of silicon nitride plug filling upon the silicon substrate.
Insulation Material Posts by Lift-Off—wherein said alignment posts are formed by the process of insulation material lift-off upon the said optical interference layer OIL.
Polyimide Posts by Photosensitive Etching—wherein said alignment posts are formed by the process of polyimide photosensitive etching upon the OIL.
REFERENCES:
patent: 4763995 (1988-08-01), Katagiri et al.
patent: 4827870 (1989-05-01), Lee
patent: 5379139 (1995-01-01), Sato et al.
patent: 5498925 (1996-03-01), Bell et al.
patent: 5581378 (1996-12-01), Kulick et al.
patent: 5597736 (1997-01-01), Sampsell
patent: 5706067 (1998-01-01), Colgan et al.
patent: 5744824 (1998-04-01), Kousai et al.
patent: 5748828 (1998-05-01), Steiner et al.
patent: 5764324 (1998-06-01), Lu et al.
patent: 5801800 (1998-09-01), Wright et al.
patent: 5831710 (1998-11-01), Colgan et al.
patent: 5982472 (1999-11-01), Moore
patent: 6027999 (2000-02-01), Wong
patent: 6051446 (2000-04-01), Moore et al.
patent: 6061114 (2000-05-01), Callegari et al.
patent: 6124912 (2000-09-01), Moore
patent: 6252999 (2001-06-01), Haskell et al.
patent: 6266121 (2001-07-01), Shigeta et al.
patent: 6449024 (2002-09-01), Hirakata et al.
Kong Sik On
Rajgopal Rajan
Wong George
Chartered Semiconductor Manufacturing Ltd.
Pike Rosemary L.S.
Saile George O.
Vockrodt Jeff
Zarabian Amir
LandOfFree
Photolithographic methods for making... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Photolithographic methods for making..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Photolithographic methods for making... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3357790