Television – Camera – system and detail – Solid-state image sensor
Reexamination Certificate
1998-12-30
2003-09-23
Garber, Wendy R. (Department: 2612)
Television
Camera, system and detail
Solid-state image sensor
C348S301000, C348S241000
Reexamination Certificate
active
06624850
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to the field of solid state photo-sensors and imagers referred to as Active Pixel Sensors (APS) that have active circuit elements associated with each pixel, and more specifically to Solid State Imagers that employ correlated double sampling (CDS).
BACKGROUND OF THE INVENTION
APS are solid state imagers wherein each pixel contains the typical solid state pixel elements including a photo-sensing means, reset means, a charge to voltage conversion means, and additionally all or part of an amplifier. The photocharge collected within the pixel is converted to a corresponding voltage or current within the pixel as discussed in prior art documents such as “Active Pixel Sensors: Are CCD's Dinosaurs?”, SPIE Vol. 1900-08-8194-1133 July 1993, by Eric Fossum. APS devices have been operated in a manner where each line or row of the imager is selected and then read out using a column select signal as discussed by E. Fossum in “Active Pixel Sensors: Are CCD's Dinosaurs?”, SPIE Vol. 1900-08-8194-1133 July 1993 and by R. H. Nixon, S. E. Kemeny, C. O. Staller, and E. R. Fossum, in “128×128 CMOS Photodiode-type Active Pixel Sensor with On-chip Timing, Control and Signal Chain Electronics”. Proceedings of the SPIE vol. 2415, Charge-Coupled Devices and Solid-State Optical Sensors V, paper 34 (1995). The selection of rows and columns within an Active Pixel Sensor is analogous to the selection of words and bits in memory devices. Here, the selection of an entire row would be analogous to selecting a word and the reading out of one of the columns of the Active Pixel Sensor would be analogous to selecting or enabling a single bit line within that word. Conventional prior art photogate devices teach architectures employing 4 transistor (4T) designs, where the 4 transistors are typically the Photogate, Row Select, Reset, and Source Follower Amplifier transistors. While this architecture provides the advantages of yielding APS devices having the capability to easily perform CDS an provide low readout noise, these 4T pixels suffer from low fill factor. Fill factor is the percentage of pixel area that is devoted to the photosensor. Each has associated contact regions and signal buses. Since these contact regions are placed in each pixel, and contact regions typically consume a large amount of pixel area due to the overlap of metal layers required, inclusion of theses contact regions in each pixel reduces the fill factor for the pixel because it takes up area that could otherwise be used for the photodetector. Connection to each of these components to the appropriate timing signal is done by metal buses that traverse the entire row of pixels. These metal buses are optically opaque and can occlude regions of the photodetector in order to fit them into the pixel pitch. This also reduces the fill factor of the pixel. Decreasing the fill factor reduces the sensitivity and saturation signal of the sensor. This adversely affects the photographic speed and dynamic range of the sensor, performance measures that are critical to obtaining good image quality.
Prior art devices employing three transistor (3T) based pixels have a higher fill factor than 4T pixels, but these 3T pixels cannot easily perform CDS. Sensors that perform CDS employing 3 transistor based pixels typically first read out and store an image frame comprising a reset level for each pixel on the sensor. Next the signal frame is captured and read out. The reset level frame stored in memory must then be subtracted from the signal frame at each pixel to provide a pixel signal level that is referenced to the pixel reset level prior to integration. This requires an extra frame of memory in the imaging system and an extra step in the digital signal processing chain, thus adversely affect the speed, size and cost of the system.
Typical prior art Photogate APS pixels are shown in
FIGS. 1
a
and
1
b
. The pixel in
FIG. 1
a
is a prior art 4 transistor pixel that comprises: a photogate photodetector (PG) and transfer transistor (TG); floating diffusion (FD); reset transistor with a reset gate (RG); row select transistor with a row select gate, (RSG); and a source follower input signal transistor (SIG). The pixel in
FIG. 1
b
is also a prior art 4 transistor pixel and where the TG is replaced by a virtual TG where a separate polysilicon gate and associated contact and signal bus is not required. As stated above these 4 transistor pixels provide low readout noise with CDS by inclusion of an extra transistor per pixel. However the area required to implement the 4
th
transistor reduces the fill factor of the pixel compared to the 3 transistor pixel.
It should be readily apparent that there remains a need within the art to provide an alternate pixel architecture that has higher fill factor, and the capability to perform CDS without the need to capture and store entire frames of image data.
SUMMARY OF THE INVENTION
The present invention provides a high fill factor Photogate Active Pixel Architecture with the capability to perform Correlated Double Sampling, (CDS). The functionality of a 4 transistor pixel is maintained while eliminating the separate row select transistor. This is done by using the PG control signal as the Row Select signal for the same row. The preferred embodiment of the invention employs a floating diffusion as the charge to voltage conversion node and specifically envisions embodiments wherein the source of the reset transistor is a floating diffusion. The invention further employs a first predetermined signal to the photogate control bus and a second predetermined signal connected to the reset gate thus enables resetting of the charge to voltage conversion node to a predetermined first potential that connects the amplifier to the output signal column bus.
The present invention provides these features by providing an Active Pixel Sensor having a plurality of pixels with at least one pixel comprising: a photogate photodetector operatively connected to a charge to voltage conversion node; a reset transistor having a source that is connected to the charge to voltage conversion node; a reset gate on the reset transistor connected to a reset control bus and a drain on the reset transistor connected to the photogate and a photogate control bus; an amplifier operatively connected to the charge to voltage conversion node.
ADVANTAGEOUS EFFECT OF THE INVENTION
The present invention provides a Photogate Active Pixel sensor with true Correlated Double Sampling (CDS) using only three transistors resulting in a higher fill factor. The advantage gained is high fill factor and lower temporal noise. No disadvantages are foreseen.
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“Active Pixel Sensors: Are CCD's Dinosaurs?” by Eric R. Fossum. Jet Propulsion Laboratory, California Institute of Technology. SPIE vol. 1900.
“A {fraction (1/4 )} Inch 330k Square Pixel Progressive Scan CMOS Active Pixel Image Sensor” by Eiji Oba et al. 1997 IEEE International Solid-State Circuits Conference. Session 11, Paper FA 11.1.
“Technology and Device Scaling Considerations for CMOS Imagers” by Hon-Sum Wong. IEEE Transactions on Electron Devices, vol. 43, No. 12, Dec. 1996.
“128×128 CMOS Photodiode-Type Active Pixel Sensor with On-Chip Timing, Control and Signal Chain Electronics” by R.H. Nixon et al. Center for Space Microelectronic Technology, Jet Propul
Eastman Kodak Company
Garber Wendy R.
Watkins Peyton C.
Whipkey Jason
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