Photoelectric conversion device

Batteries: thermoelectric and photoelectric – Photoelectric – Panel or array

Reexamination Certificate

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C136S258000, C136S256000, C136S244000, C257S431000, C257S461000, C257S443000, C438S063000

Reexamination Certificate

active

06620996

ABSTRACT:

This application is based on applications Nos. 2000-159043, 2000-161267, 2000-194395, 2000-198451, 2000-227640, 2000-258027 filed in Japan, the content of which is incorporated hereinto by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a photoelectric conversion device, in particular, to a photoelectric device using numerous crystalline semiconductor particles. The photoelectric conversion device according to this invention is utilized suitably in solar cells.
2. Description of the Related Art
Advent of a next-generation, low-cost solar cell that allows the quantity of silicon material to be small has been eagerly awaited.
Conventional photoelectric devices in which granular or spherical silicon crystal grains are used are shown in
FIGS. 14-17
.
The photoelectric conversion device in
FIG. 14
comprises a low melting-point metal (tin) layer
108
formed on a substrate
101
, numerous crystalline semiconductor particles
103
of a first conductivity-type deposited on the low melting-point metal layer
108
, and an amorphous semiconductor layer
107
of a second conductivity-type formed on the crystalline semiconductor particles
103
(Refer to Japanese Patent No. 2641800).
In addition, an insulating layer
102
(SiO
2
) is interposed between the amorphous semiconductor layer
107
and the low melting-point metal layer
108
.
Since the amorphous semiconductor layer
107
serves as the second conductivity-type semiconductor layer in the photoelectric device in
FIG. 14
, the thickness of the amorphous semiconductor layer
107
needs to be small taking the great light absorption thereof into account. For this reason, the film thickness locally varies when the amorphous semiconductor layer
107
is formed along the surfaces of the crystalline semiconductor particles
103
. In general, the film thickness in the part on the crystalline semiconductor particles
103
is large, and that in the side of the crystalline semiconductor particles
103
is small.
The thin films fail to sufficiently cover the whole surfaces of the crystalline semiconductor particles
103
making it difficult to form a PN-junction along the outer contours of the crystalline semiconductor particles
103
.
Also, the small thickness of the amorphous semiconductor layer
107
makes the tolerance to defects small also necessitating stricter management of the cleaning process and the production environment.
In addition, since the thin amorphous semiconductor layer
107
has high resistance, a transparent conductive film needs to be formed as the upper electrode on the amorphous semiconductor layer
107
, which results in a high manufacturing cost.
In this device, since the insulating layer
102
is formed after securing the particles
103
on the low melting-point metal layer
108
, the insulating layer
102
is formed not only on the low melting-point metal layer
108
but also on the particles
103
. Accordingly, the insulating layer
102
on the particles
103
needs to be removed before the formation of the amorphous semiconductor layer
107
.
Although it is possible to form the amorphous semiconductor layer
107
after grinding the crystalline semiconductor particles
103
and the insulating layer
102
so as to be exposed in a flat surface, this necessitates addition of a grinding process and a cleaning process for removing chips after the grinding. Furthermore, when there is unevenness in the heights of crystalline semiconductor particles
103
, the PN-junction area also locally varies causing insufficient properties. As a result, the device suffers high costs and low conversion efficiency.
Also, the low melting point of the low melting-point metal layer
108
makes its reliability low.
Regarding the auxiliary electrode, the Japanese Patent No. 2641800 only describes that an appropriate metal collector electrode is formed, and it includes no specific description about preferred electrodes.
FIG. 15
discloses a photoelectric conversion device in which an upper aluminum foil
111
is formed with openings
111
a
with which silicon balls
110
are contacted. Each of the silicon balls
110
has a n-type surface portion
110
b
formed on a p-type core
110
a
. The n-type surface portions
110
b
in the rear surfaces of the silicon balls
110
are removed, and the aluminum foil
111
is coated with an oxide layer
114
. The oxide layer
114
in the rear surfaces of the silicon balls
110
are removed so that the p-type cores
110
a
are contacted with a lower aluminum foil
113
(Japanese Unexamined Patent publication S61-124179(A)).
The device in
FIG. 15
requires production of the silicon balls
110
having the n-type surface portions
110
b
formed on the p-type cores
110
a.
In addition, the openings
111
a
need to be formed in the aluminum foil
111
so that the silicon balls
110
are pressed into and contacted with the openings
111
a.
This requires the silicon balls
110
to be uniform in diameter, resulting in high cost manufacture.
The photoelectric conversion device in
FIG. 15
has another problem in that when the silicon balls
110
are contacted with the lower aluminum foil
113
, the lower aluminum foil
113
, the substrate, melts when the junction temperature increases to no less than 577° C., which is the eutectic temperature of aluminum and silicon. As a result, the silicon balls
110
penetrate the aluminum foil
113
.
FIG. 16
discloses a method in which semiconductor microcrystalline grains
123
are deposited on a substrate
120
, and then fused, saturated and gradually cooled so that the semiconductor is grown by liquid phase epitaxial growth, thereby forming a first conductivity-type polycrystalline thin film
123
(Japanese Patent Publication No.H8-34177(B)).
FIG. 16
shows a low melting-point metal film
121
comprising a metal such as Sn, a high melting-point metal film
122
comprising a metal such as Mo, a second conductivity-type polycrystalline or amorphous semiconductor layer
124
, and a transparent conductive film
125
.
In the photoelectric conversion device in
FIG. 16
, the low melting-point metal
121
mixes into the first conductivity-type liquid phase epitaxial polycrystalline layer
123
, thereby deteriorating the performance of the polycrystalline layer
123
. In addition, due to the absence of an insulator between the transparent conductive film
125
and the high melting-point metal film
122
, short circuit is likely to occur.
FIG. 17
discloses a photoelectric conversion device, wherein an aluminum film
132
is formed on the surfaces of a steel substrate
131
, the aluminum film
132
being contacted with crushed silicon particles
133
, and then an insulating layer
136
, n-type silicon portions
134
, and a transparent conductive layer
135
are sequentially formed (U.S. Pat. No. 4,514,580).
In this photoelectric device, since the aluminum film
132
is formed on the surface of the steel substrate
131
, the aluminum film
132
is oxidized first, and the steel substrate
131
is oxidized thereafter. This makes the reliability of this photoelectric conversion device low, and the life thereof short.
In order to secure the reliability, the aluminum film
132
needs to be thickened. However, when the aluminum film
132
is thickened, the crushed silicon particles
133
in contact with it need to have diameters increased accordingly, which is a problem.
There is a description in the disclosure of the photoelectric conversion device in
FIG. 17
meaning that the electrode may comprise any desired pattern of bus bars and fingers. However, it has no specific description of preferred auxiliary electrodes.
It is an object of this invention to provide a photoelectric conversion device with excellent properties.
BRIEF SUMMARY OF THE INVENTION
A photoelectric conversion device according to the present invention comprises: first conductivity-type crystalline semiconductor particles being deposited on and in contact with a substrate in a large number; an insulator formed in an area on the substrate where the crystalline semicon

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