Radiation imagery chemistry: process – composition – or product th – Radiation modifying product or process of making – Radiation mask
Reexamination Certificate
2002-04-02
2004-11-23
Letscher, Geraldine (Department: 1752)
Radiation imagery chemistry: process, composition, or product th
Radiation modifying product or process of making
Radiation mask
C430S022000, C430S311000, C430S312000, C430S313000, C430S322000
Reexamination Certificate
active
06821687
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to a method of manufacturing a semiconductor device having a dual damascene structure in which a via for electrically coupling a lower wiring layer and an upper wiring layer and the upper wiring layer are buried within an interlayer insulating film. More particularly, the present invention relates to a photo mask used when a via hole for forming a via and a wiring trench or groove for forming the wiring conductor of the upper wiring layer are opened, and to a method of manufacturing a semiconductor device which uses such photo mask.
BACKGROUND OF THE INVENTION
According to an increase in an integration degree and a packing density of a semiconductor device, a dual damascene structure has become often used. In the dual damascene structure, a via for electrically coupling a lower wiring layer and an upper wiring layer and a wiring conductor of the upper wiring layer are buried within an interlayer insulating film. In the dual damascene structure, a via hole which is an opening for forming a via that electrically couples with a lower wiring layer and a wiring trench or groove for forming a wiring conductor of an upper wiring layer that extends in an area including the via are formed one after another in an interlayer insulating film by using a photolithography technology. Thereafter, the opening of the via hole and the wiring groove are filled with a wiring material. The upper surface of the workpiece substrate is then polished flat and the wiring material on the interlayer insulating film is removed. Such manufacturing method is described, for example, in Japanese patent laid-open publication No. 2000-150641.
FIGS. 9A-9E
are cross sectional views each illustrating a structure of a workpiece obtained during a process of fabricating a dual damascene structure according to a conventional technology, which is substantially the same as the technology described in the above-mentioned Japanese patent laid-open publication.
First, as shown in
FIG. 9A
, a groove formed in a base insulating film or layer
121
on a semiconductor substrate not shown in the drawing is filled with a metal such as copper and the like, and the upper surface is planarized or flattened to form a lower wiring layer
122
having predetermined wiring patterns. On the lower wiring layer
122
, an Si
3
N
4
film
123
, an SiO
2
film
124
, an SiC film
125
, an HSQ film
126
and an SiO
2
film
127
are formed one after another in this order, thereby an interlayer insulating film
128
comprising these film is formed.
As shown in
FIG. 9B
, by using a first photolithography process in which a first photo resist PR
11
is used, the interlayer insulating film
128
is selectively etched to form a via hole
129
in an area where a via or a via conductor is to be formed such that the via hole
129
reaches the Si
3
N
4
film
123
.
Next, as shown in
FIG. 9C
, by using a second photolithography process in which a second photo resist PR
12
is used, the interlayer insulating film
128
is selectively etched to form a wiring groove
130
in a predetermined area which includes the via hole
129
and where the wiring groove
130
is to be formed such that the wiring groove
130
reaches the SiC film
125
.
Thereafter, to obtain the structure shown in
FIG. 9D
, the portion of the Si
3
N
4
film
123
at the bottom surface of the via hole
129
is selectively etched and removed to expose the surface of the lower wiring layer
22
. A wiring material
131
comprising a metal such as copper and the like is sputtered on whole area of the workpiece to fill the via hole
129
and the wiring groove
130
with the metal. Then, the surface of the workpiece is planarized by using a CMP (chemical mechanical polishing) method, and a structure is obtained in which the wiring material
131
remains and is buried only within the via hole
129
and the wiring groove
130
. Thereby, the via
132
which is electrically coupled with the lower wiring layer
122
and the upper wiring layer
133
which is electrically coupled with the via
132
and thus the lower wiring layer
122
are formed.
In this way, when the dual damascene structure is fabricated, the first and second photolithography processes are required. Therefore, in the first photolithography process, an alignment technology is required in which the location or position of the via hole
129
is aligned with respect to the location of the lower wiring layer
22
. Also, in the second photolithography process, an alignment technology is required in which the location of the wiring groove
130
is aligned with respect to the location of the via hole
129
. In order to perform these alignment, it is necessary to provide alignment marks in first and second photo masks which are used for exposing, developing and patterning first and second photo resist films used in the first and second photolithography processes, respectively. In the first photolithography process, the alignment mark of the first photo mask is aligned with a lower layer alignment mark which is formed simultaneously with the lower wiring layer. In the second photolithography process, the alignment mark of the second photo mask is aligned with an alignment hole which is formed simultaneously with the via hole by using the alignment mark of the first photo mask.
FIG. 10A
is a schematic plan view showing an alignment mark used when an alignment is performed in the first photolithography process.
FIG. 10B
is a cross sectional view of a workpiece of a semiconductor device formed by using the alignment mark of FIG.
10
A.
FIG. 10C
is a cross sectional view illustrating a via alignment hole formed simultaneously with a via hole in the first photolithography process.
As shown in
FIGS. 10A and 10B
, by using a part of the lower wiring layer
122
, a lower layer alignment mark DM
11
is previously formed which has a square frame like shape. Also, in the first photo mask, a first via alignment mark M
11
is formed which has a square shape and which is to be located at the central position of the lower layer alignment mark DM
11
. By using the first photo mask, the first photolithography process is performed, and by using the first photo resist pattern PR
11
which is obtained by exposing and developing the first photo resist, the via hole
129
is opened in the interlayer insulating film
128
. In this case, the first photo resist pattern PR
11
formed by the first via alignment mark M
11
and the lower layer alignment mark DM
11
are optically scanned by a misalignment measuring equipment or apparatus in a direction shown by an arrow S
11
in FIG.
10
A. The reflection of light obtained from the optical scanning is detected and a signal output V
11
shown in the upper portion of
FIG. 10B
is obtained. Based on the signal output V
11
, a relative locational difference between the central location C
21
of the first photo resist pattern PR
11
by the first via alignment mark M
11
and the central location C
22
of the lower layer alignment mark DM
11
is detected, and thereby alignment between the first via alignment mark M
11
and the lower layer alignment mark DM
11
is performed.
FIG. 11A
is a schematic plan view showing an alignment mark used when an alignment is performed in the second photolithography process.
FIG. 11B
is a cross sectional view of a workpiece of a semiconductor device formed by using the alignment mark of FIG.
11
A.
FIG. 11C
is a cross sectional view illustrating a upper layer alignment hole formed simultaneously with a wiring groove in the second photolithography process.
In this case, as shown in
FIGS. 11A and 11B
, in the first photo mask used in the first photolithography process, a second via alignment mark M
12
is previously formed which has a square frame like shape. Thereby, the second via alignment hole MH
12
is opened in the interlayer insulating film
128
simultaneously with the forming of the via hole
129
. Also, in the second photo mask, an upper layer alignment mark UM
11
is formed which has a square shape and whic
Hamanaka Nobuaki
Oda Noriaki
Shiba Kazutoshi
Yokoyama Takashi
Letscher Geraldine
NEC Electronics Corporation
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