Photo-imaged stress management layer for semiconductor devices

Details Photo-imaged stress management layer for semiconductor devices Photo-imaged stress management layer for semiconductor devices

2007-06-19

2007-06-19

Dang, Phuc T. (Department: 2818)

Semiconductor device manufacturing: process

Having magnetic or ferroelectric component

C257S295000

Reexamination Certificate

active

11071940

ABSTRACT:
A photo-imaged stress management layer for a semiconductor device is described. The stress management layer is located on an outer surface of a semiconductor device and may be patterned to address certain stress compensation requirements of the semiconductor device. The stress management layer may be manufactured onto the semiconductor device using a photolithographic procedure that allows both simple and complex patterns to be realized.

REFERENCES:
patent: 6849391 (2005-02-01), Yamaguchi et al.
patent: 6884662 (2005-04-01), Chen et al.

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