Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2001-07-17
2004-02-24
Karlsen, Ernest (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S501000, C324S719000
Reexamination Certificate
active
06696847
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to testing of semiconductor structures, and more particularly, to electrical linewidth measurement.
2. Discussion of the Related Art
The paper “Characterization of line width variation” by Alfred K. Wong, Antoinette F. Molless, Timothy A. Brunner, Erik Coker, Robert H. Fair, George L. Mack and Scott M. Mansfield, Optical Microlithography XIII, Proceedings of SPIE Vol. 4000(2000), pages 184-191, discusses the importance of controlling line width in semiconductor devices. As pointed out therein, control of line width variation is of the increasing concern as device critical dimension (CD) shrinks rapidly and optical lithography is used for printing features at an ever smaller fraction of the wavelength of light.
The paper “Electrical Critical Dimension Metrology for 100-nm Linewidths and Below”, Andrew Grenville, Brian Coombs, John Hutchinson, Kelin Kuhn, David Miller and Patrick Troccolo, Optical Microlithography XIII, Proceedings of SPIE Vol. 4000(2000), pages 452-459, describes electrical line width measurement for performing critical dimension measurements, setting forth the importance of understanding the relationship between physical line width and electrical line width, which will now be described.
FIG. 1
herein shows a typical electrical critical dimension (ECD) structure
20
for electrically measuring the width of a line
22
, for example, a polysilicon line disposed on a silicon dioxide body
24
in turn provided on a crystalline silicon wafer
26
(FIGS.
1
-
4
). The structure typically has test pads
28
,
30
,
32
,
34
connected to the line
22
to be tested, and appropriate probes may be connected to the pads
28
,
30
,
32
,
34
to run a variety of electrical tests, including application of electrical potential across the line
22
, and measurement of current through the line
22
. In accordance with the Grenville et al. paper, typically, ion implant
36
(
FIG. 2
) and anneal steps are undertaken to increase conductivity of the line
22
, and then an electrical potential is applied to the line
22
and current therethrough is measured to indicate the width of the line
22
. Due to dopant out diffusion
37
from the line
22
(FIG.
3
), only the area
38
indicated as shown in
FIG. 4
(having a width W
1
, less than the physical width W
2
of the line
22
) remains conductive. Thus, there exists a significant difference between physical line width W
2
and electrically measured line width W
1
. Furthermore, with the amount of dopant lost through the walls of a line being substantially constant per unit of wall area, the relative loss of dopant for a narrower line
40
(
FIGS. 5-7
) will be greater than for a wider line
22
. That is, after ion implantation
42
(
FIG. 5
) and anneal and dopant out diffusion
44
(FIG.
6
), only the area
46
(having width W
3
) indicated as shown in
FIG. 7
remains electrically conductive. The width W
3
is a smaller proportion of the physical width W
4
of the line
40
than is the case in the structure of
FIG. 4
, i.e., W
3
/W
4
<W
1
/W
2
.
FIG. 1
of the Grenville et al. paper discusses the bias between physical line width and electrically measured line width. While a bias of 90nm is indicated for past processes, this has previously not been a significant problem, since line widths of interest were 100 nm or larger. However, with line widths becoming smaller, the process as disclosed in the Grenville et al. paper has as its goal the reduction of this bias by varying the dopant and anneal process. Grenville et al. point out, however, that the penalty for practicing the disclosed process is increased sheet resistivity (on the order of fivefold). Furthermore, while the process appears to reduce the bias described above, a substantial bias still exists, and Grenville et al. point out that the ultimate goal would be to completely eliminate this bias, so as to eliminate the problems attendant thereto.
Therefore, what is needed is a process for electrically measuring linewidth wherein the problems associated with bias between physical linewidth and electrically measured linewidth are avoided.
SUMMARY OF THE INVENTION
In the present method of electrically testing the width of a line, a short pulse of laser energy is applied to the line to generate conductive electrons. An electrical potential is applied to the line to cause generated conductive electrons to flow, and current flow is measured to determine the width of the line.
The present invention is better understood upon consideration of the detailed description below, in conjunction with the accompanying drawings. As will become readily apparent to those skilled in the art from the following description, there is shown and described an embodiment of this invention simply by way of the illustration of the best mode to carry out the invention. As will be realized, the invention is capable of other embodiments and its several details are capable of modifications and various obvious aspects, all without departing from the scope of the invention. Accordingly, the drawings and detailed description will be regarded as illustrative in nature and not as restrictive.
REFERENCES:
patent: 4320289 (1982-03-01), White et al.
patent: 6043893 (2000-03-01), Treiman et al.
patent: 6066952 (2000-05-01), Nowak et al.
patent: 6160407 (2000-12-01), Nikawa
patent: 6320396 (2001-11-01), Nikawa
patent: 6456082 (2002-09-01), Nowak et al.
Characterizationof Line Width Variation, Alfred K. Wong, Antoinette F. Molless, Timothy A. Brunner, Eric Coker, Robert H. Fair, George L. Mack, Scott M. Mansfield, Optical Microlithography XIII, Proceedings of SPIE vol. 4000 (month unavailable)(2000), pp. 184-191.
Electrical Critical Dimension Metrology for 100-nm Linewidths and Below, Andrew Grenville, Brian Coombs, John Hutchinson, Kelin Kuhn, David Miller, Patrick Troccolo, Optical Microlithography XIII, Proceedings of SPIE vol. 4000 (month unavailable)(2000), pp. 452-459.
Kye Jong-wook
LaFontaine Bruno M.
Levinson Harry
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