Phase synchronization pull-in system in bit error detecting appa

Details Phase synchronization pull-in system in bit error detecting appa Phase synchronization pull-in system in bit error detecting appa

1990-03-16

1992-06-16

Baker, Stephen M.

Excavating

371 54, G06F 1540, H04L 100

Patent

active

051230208

ABSTRACT:
A phase synchronization pull-in system used in a bit error detecting apparatus includes a monitored circuit for inputting an input signal and processing the input signal when an operation of the monitored circuit is to be monitored, a standard circuit for processing an output of the monitored circuit inversely to the processing in the monitored circuit, a phase synchronization circuit for inputting the input signal of the monitored circuit and adjusting a first delay time of the input signal so that the first delay time coincides with a second delay time of the output of the standard circuit corresponding to the input signal, a bit error detecting circuit for detecting a difference between the input signal, after being delayed through a variable delay circuit, and the output of the standard circuit, bit by bit, and a controller for controlling the adjusting of the first delay time, a monitoring operation, and a phase synchronization pull-in operation. In the phase synchronization pull-in operation, the first delay time is obtained in the phase synchronization circuit based on whether or not a bit error rate measured by setting the delay time is higher than a predetermined value. The controller determines whether or not more than one possible value of the first delay time enables a successful phase synchronization pull-in, and carries out the monitoring operation when a successful phase synchronization pull-in is successfully carried out for only one value of the first delay time.

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