Pulse or digital communications – Equalizers – Automatic
Reexamination Certificate
2001-02-26
2003-11-25
Vo, Don N. (Department: 2631)
Pulse or digital communications
Equalizers
Automatic
C375S263000, C375S362000, C360S065000
Reexamination Certificate
active
06654413
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a phase synchronization method to synchronize phases, a phase synchronization circuit, and a read channel circuit in an extended partial response regeneration system using (1, 7) RLL codes.
BACKGROUND ART
For a storage device, such as a magnetic recording device and an optical recording device, high density recording is demanded. Therefore, in a magnetic recording device, a partial response recording system is used. For partial response recording, 8/9 codes are used. 8/9 codes are codes that convert 8 bits to 9 bits. 8/9 codes are codes where the number of “0s” between “1” and “1” is a minimum of 0 and a maximum of 4.
In this magnetic recording device, high-density recording can be implemented by decreasing the size of magnetic particles of the magnetic recording medium. However, if the size of magnetic particles is decreased, thermal relaxation, where the direction of magnetic domain changes due to heat, tends to occur. This thermal relaxation deletes magnetic information. Therefore (1, 7) RLL codes with low recording frequency are used instead of using 8/9 codes.
(1, 7) RLL codes are codes where the number of “0s” between “1” and “1” is a minimum of 1 and a maximum of 7. Since one “0” is always inserted between “1” and “1”, recording frequency is decreased. By using this codes, the loss of magnetic information by thermal relaxation can be prevented.
For the (1, 7) RLL codes, an extended partial response recording system, such as EPR (Extended Partial Response) and EEPR (Extended Extended Partial Response) having a low frequency spectrum, is used. In such a system, a phase synchronization method for synchronizing clocks stably is demanded.
FIG. 17
is a block diagram depicting a prior art,
FIG. 18
is a spectrum diagram of a partial response, and FIG.
19
(A), FIG.
19
(B) and FIG.
19
(C) are diagrams depicting partial responses.
FIG. 17
shows a recording channel and a read channel of a partial response magnetic recording. As
FIG. 17
shows, the recording channel has a coder
93
that converts recording data to (1, 7) codes. The output of the coder
93
is pre-coded by the pre-coder
94
, then is written to the magnetic disk
91
by the magnetic head
90
via the amplifier
95
.
The recorded data is read from the magnetic disk
91
by the magnetic head
90
. The output of the magnetic head
90
is input to the PR equalizer
98
via the amplifier
97
. The PR equalizer
98
executes partial response equalization. The output is sampled by the sampler
99
. An analog/digital converter is normally used for the sampler
99
.
The output of the sampler
99
is input to a five-value judgment unit
100
for five-value judgment. The five-value judgment output is input to the maximum-likelihood detector
101
where the maximum-likelihood value is detected. And the detection signal is input to the (1−D) equalizer
102
that has a (1−D) equalization characteristic. The (1−D) equalizer
102
cancels the characteristic of the pre-coder
94
. Furthermore, the output of the (1−D) equalizer
102
is decoded by the (1, 7) decoder
103
. By doing this, regeneration data is obtained.
The judgment output of the five-value decision unit
100
and the sample output are input to the phase error computing unit
104
. The phase error computing unit
104
computes the phase error from the judgment output and the sample output. This error is smoothed by the loop filter
105
. And the voltage control oscillator (VCO)
106
generates a clock at a frequency (phase) according to the output of the loop filter
105
. This clock is used as a sampling clock of the sampler
99
.
Since these (1, 7) RLL codes are codes having at least one “0” between “1” and “1”, recording frequency is low. So even if high-density recording is executed, loss of data by thermal relaxation can be prevented.
As
FIG. 18
shows, in a partial response, the spectrum of EPR-
4
(Extended Partial Response Class-
4
) has a lower frequency than the spectrum of PR-
4
(Partial Response Class-
4
). In other words, EPR-
4
has a higher gain at low frequency. And EEPR-
4
(Extended Extended Partial Response Class-
4
) has an even lower frequency spectrum.
Since (1, 7) RLL codes have a low frequency spectrum, EPR-
4
and EEPR-
4
, where low frequency gain is high, are appropriate. When D is the delay operator, and PR-
4
is given by the transfer function (1−D)·(1+D), then EPR-
4
is given by the transfer function (1−D)·(1+D)·(1+D). And EEPR-
4
is given by (1−D)·(1+D)·(1+D)·(1+D).
As a modification of EPR-
4
, MEPR-
4
(Modified Extended Partial Response Class-
4
) given by the transfer function (1−D)·(1+D+D
2
) and MMEPR-
4
(Modified Modified Extended Partial Response Class-
4
) given by the transfer function (1−D)·(1+1.5D+D
2
) are known. As a modification of EEPR-
4
, MEEPR-
4
(Modified Extended Extended Partial Response Class-
4
) given by the transfer function (1−D)·(1+D)·(1+D+D
2
) and MMEEPR-
4
(Modified Modified Extended Extended Partial Response Class-
4
) given by the transfer function (1−D)·(1+D)·(1+1.5D+D
2
) are known.
This partial response in a broad sense, which includes the transfer formula (1−D)·(1+(1+a)D+D
2
), is called an “extended partial response”. Here a≧0. As FIG.
19
(A) shows, the regenerated solitary wave in PR-
4
indicates three states, 1, 0 and −1. The regenerated solitary wave of EPR-
4
(MEPR-
4
), on the other hand, indicates five states, 2 (1.5), 1, 0, −1 and −2 (−1.5), as shown in FIG.
19
(B). Also as FIG.
19
(C) shows, the regenerated solitary wave of EEPR-
4
(MMEEPR-
4
) indicates five states, 2 (1.5), 1, 0, −1 and −2 (−1.5).
In this way, the extended partial response in a broad sense has five states. In the extended partial response, the phase synchronization operation has been executed as follows.
As
FIG. 20
shows, the magnetic disk
90
has an acquisition area
111
and a data area
112
in each sector
110
. In the acquisition area
111
, data to train each part of the regeneration circuit is written. In this acquisition area
111
, the clock acquisition pattern (phase synchronization pattern) is recorded.
As
FIG. 17
shows, an acquisition pattern is read at acquisition. And the state is judged by comparing the amplitude of the acquisition pattern and the slice level. A phase error is computed from the judgment value and the sampling output. The phase of the clock of the voltage control oscillator
106
is synchronized by this computed phase error. At tracking to read the data area, the state of a signal is judged by comparing the amplitude of the read data of the data area
112
with the slice level. From the judgment value and the sample output, a phase error is computed, and the phase of the clock of the voltage control oscillator
106
is synchronized.
For this conventional acquisition pattern, the pattern of a 4T period (T is the sampling interval) has been used for PR-
4
, as shown in FIG.
21
. This pattern is a continuous pattern of “1s” in 8/9 codes.
Also conventionally, it is necessary to judge the read signal to be one of five values to compute the phase error, since an extended partial response takes five value states.
At first, in the case of (1, 7) RLL codes, where 2 bits are converted to 3 bits, encoding efficiency is poor compared with 8/9 codes, where 8 bits are converted to 9 bits. Therefore compared with 8/9 codes, track recording density must be increased to record in the case of (1, 7) RLL codes. If a conventional acquisition pattern with a 4T period is used when the track recording density is high like this, the amplitude of the regeneration signal for clock acquisition drops due to inter-symbol interference. As a result, S/N drops and clock acquisition becomes difficult.
Secondly, if (1, 7) RLL codes and the extended partial response in a broad sense are combined, there are five signal states, as described in FIG.
Greer Burns & Crain Ltd.
Vo Don N.
LandOfFree
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