Phase-synchronization method and circuit for establishing a...

Dynamic magnetic information storage or retrieval – Converting an analog signal to digital form for recording;...

Reexamination Certificate

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Details

C360S051000, C341S111000, C375S371000, C331S018000

Reexamination Certificate

active

06510013

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention generally relates to the art of phase-synchronization of signals and more particularly to a phase-synchronizing circuit and method for use in various electronic apparatuses including magnetic disk device.
Particularly, the present invention relates to a phase-synchronizing circuit and method in which the time needed for establishing a phase synchronization is minimized.
FIG. 1
shows an example of a magnetic disk device
1
according to a related art.
Referring to
FIG. 1
, the magnetic disk drive
1
includes a magnetic disk
2
accommodated in an enclosure
10
having a cover
11
and stores information on the magnetic disk
2
in the form of concentric tracks. The magnetic disk
2
is mounted on a spindle motor
6
for rotation, and a floating magnetic head
5
scans over the surface of the magnetic disk
5
. The magnetic head
5
is mounted at an end of a swing arm
7
, wherein the arm
7
is connected to a voice coil motor
8
and the voice coil motor
8
actuates the arm
7
for swinging motion. With the swinging motion of the arm
7
thus caused by the voice coil motor
8
, the magnetic head
5
scans over the surface of the magnetic disk
2
generally in a radial direction thereof. Thereby, the magnetic head
5
is controlled so as to trace a desired track on the disk
2
.
The voice coil motor
8
is supplied with an electric signal from a read/write amplifier
9
for actuating the arm
7
, while the read/write amplifier
9
further supplies an electric signal to the magnetic head
5
via the arm
7
for writing or reading of information on or from the magnetic disk
2
. Thus, in response to the electric signal, the magnetic head
5
senses, or alternatively induces, a magnetization on the magnetic disk
2
and writing or reading of information is achieved on or from the magnetic disk
2
.
It should be noted that the electric signal thus supplied to the magnetic head
5
from the read/write amplifier
9
corresponds to the data created and supplied from a host device (not shown), wherein the host device supplies the data to a circuit substrate
4
of the magnetic disk device
1
via a connector
3
, and the electric circuit provided on the circuit substrate
4
converts the data to the electric signal.
In the construction of
FIG. 1
, it should be noted that the magnetic disk
2
, the magnetic head
5
, the spindle motor
6
, the arm
7
, the voice coil motor
8
and the read/write amplifier
9
are accommodated in the enclosure
10
having the cover
11
.
In an example in which an operation is made in the host device for reproducing the information from the magnetic disk
2
, the data indicative of the operation is supplied to the circuit substrate
4
via the connector
3
, and the circuit substrate
4
converts the data to corresponding signals for activating the various parts of the magnetic disk device
1
including the magnetic head
5
.
In response to the electric signal thus supplied, the magnetic head
5
reads the information stored on the magnetic disk
2
. The information thus read out by the magnetic head
5
, in turn, is forwarded to the read/write amplifier
9
for amplification and further to the processing circuit provided on the circuit substrate
4
for conversion to digital data indicative of the result of the reading operation. The data thus produced by processing circuit on the circuit substrate
4
is then forwarded to the host device not illustrated via the connector
3
.
Next, a description will be made on the signal processing carried out by the processing circuit on the circuit substrate
4
.
FIG. 2
shows the construction of the magnetic disk device of
FIG. 1
in the form of a block diagram.
Referring to
FIG. 2
, the signal processing circuit on the circuit substrate
4
includes an interface (I/F)
400
, a hard disk controller (HDC) unit
401
, a read gate
402
, an AGC (automatic gain controller) unit
403
, a modulator unit
407
, a write driver unit
408
, a gain error detection unit
409
, and a sampling clock generator
410
, wherein the interface
400
converts the data supplied from the host device into corresponding signals which the electric circuits on the circuit board
4
of
FIG. 2
can handle.
In the construction of
FIG. 2
, it should be noted that the HDC unit
401
supplies the signals thus produced to corresponding circuits constituting the processing circuit on the circuit board
4
.
More specifically, in the case of operating the magnetic disk device
1
in a recording (writing) mode, the HDC unit
401
supplies the signals to the modulator
407
for modulation. In response to this, the modulator
407
produces a modulated output signal and supplies the same to the write driver unit
408
for write control operation. Thereby, desired information is written on the magnetic disk
2
by way of the magnetic head
5
, after being subjected to an encoding process conducted in the read/write amplifier
9
.
In the case of a reproducing (reading) mode, the HDC
401
unit activates the sampling clock generator
410
, the AGC unit
403
and the read/write amplifier
9
by sending thereto the electric signals.
In response to the activation, the read/write amplifier
9
reads the information recorded on the magnetic disk
2
via the magnetic head
5
and produces a decoded signal. The AGC unit
403
is supplied with the decoded signal and supplies the same to the sampling clock generator
410
for processing after automatic gain control. After the processing in the sampling clock generator
410
, the information signal is supplied to the HDC unit
401
and the HDC unit
401
supplies the processed information signal to the host device via the interface
400
and the connector
3
.
Hereinafter, the operation of the sampling clock generator
410
of
FIG. 2
will be explained in detail.
As indicated in
FIG. 2
, the sampling clock generator
410
includes an ADC (analog-to-digital converter) unit
404
, a demodulator
405
and a phase-synchronizing circuit
406
, wherein the ADC unit
404
, the demodulator
405
and the phase-synchronizing circuit
406
constitutes a phase-locked loop.
When writing or reading information to or from the magnetic disk
2
, the magnetic head
5
is first caused to scan over a specific track of the magnetic disk
2
carrying a synchronization pattern, and the information signal indicative of the synchronization pattern is picked up. After processing in the read/write amplifier
9
and the ACG unit
403
, the ADC unit
404
of the sampling clock generator
410
converts the synchronizing signal into a corresponding digital signal by sampling the synchronizing signal according to a clock signal supplied from the phase-synchronizing circuit
406
.
The digital signal thus produced is supplied to the demodulator
405
, wherein the demodulator
405
has a synchronizing signal pattern corresponding to the synchronization pattern on the magnetic disk
2
and produces a phase-error signal indicative of the phase-error of the digital signal, and hence the phase-error of the clock signal used in the ADC unit
404
, based on the comparison of the output of the ADC unit
404
with the synchronizing signal pattern held therein.
The output of the demodulator
405
indicative of the phase-error thus produced is then supplied to the phase-synchronizing circuit
406
and the phase-synchronizing circuit
406
adjusts the timing or phase of the phase synchronizing signal such that the detected phase-error is nullified.
After a synchronization is thus established for the clock signal produced by the phase-synchronizing circuit
406
, the magnetic head
5
is caused to scan over the track from which an information signal to be read out or over the track on which an information signal is to be written, and the information signal thus read out from the magnetic disk
2
is sampled, after being processed by the read/write amplifier
9
and the AGC unit
403
, in the ADC unit
404
by the clock signal produced by the phase-synchronizing circuit
406
with the desired phase synchr

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