Phase synchronization circuit and semiconductor integrated...

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing

Reexamination Certificate

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C327S152000, C327S158000

Reexamination Certificate

active

11288176

ABSTRACT:
A phase synchronization circuit comprises: a measurement delay line which includes a plurality of delay elements having different delay times and to which a first clock signal is inputted; a phase comparator line which includes a plurality of phase comparators in accordance with the measurement delay line and to which a signal from the measurement delay line and a second clock signal are inputted so as to measure a transition timing difference between the first clock signal and the second clock signal; and a generation delay line which includes a plurality of delay elements having different delay times in accordance with the measurement delay line and to which a signal from the phase comparator line and a third clock signal are inputted. The delay time of the respective delay elements is fixed.

REFERENCES:
patent: 5901190 (1999-05-01), Lee
patent: 6004453 (1999-12-01), Benham et al.
patent: 6396322 (2002-05-01), Kim et al.
patent: 6617894 (2003-09-01), Yoon et al.
patent: 6933758 (2005-08-01), Kim et al.
patent: 2005/0146365 (2005-07-01), Kim et al.
patent: 2002-152018 (2002-05-01), None
“A 2.5-ns Clock Access, 250-MHZ, 256-Mb SDRAM with Synchronous Mirror Delay” by IEEE Journal of Solid State Circuits, vol. 31, No. 11, Nov. 1996.

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