Phase synchronization circuit and method therefor for a phase lo

Details Phase synchronization circuit and method therefor for a phase lo Phase synchronization circuit and method therefor for a phase lo

1993-11-09

1996-03-05

Pascal, Robert J.

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

331 16, 331 14, 331 25, 327156, 327157, 327159, 455 76, 455260, 375376, H03L 718

Patent

active

054971268

ABSTRACT:
An improved phase synchronization circuit (301) and method therefor for a phase locked loop (300). Each of a divided reference frequency signal (206) and a feedback signal (209) is held in a predetermined state. The divided reference frequency signal (206) is enabled responsive to the phase of a reference frequency signal (115). A phase relationship between the reference frequency signal (115) and an output frequency signal (116 or 117) is determined. The feedback signal (209) is enabled responsive to enabling the divided reference frequency signal (206) and the determined phase relationship. The present invention advantageously provides a rapid and accurate phase synchronization for the PLL (300) with minimum additional hardware and without introducing phase error into the PLL (300).

REFERENCES:
patent: 4812783 (1989-03-01), Honjo et al.
patent: 4817199 (1989-03-01), Wallraff
patent: 4841255 (1989-06-01), Ohba et al.
patent: 5008629 (1991-04-01), Ohba et al.
patent: 5122678 (1992-06-01), Takeyama
patent: 5128632 (1992-07-01), Erhart et al.
patent: 5180992 (1993-01-01), Akiyama
patent: 5202906 (1993-04-01), Saito et al.
patent: 5304954 (1994-04-01), Saito et al.
patent: 5339278 (1994-08-01), Irwin et al.
"State-Preserving Intermittently Locked Loop (SPILL) Frequency Synthesizer for Portable Radio", IEEE Transactions on Microwave Theory and Techniques, vol. 37, No. 12, Dec. 1989, pp. 1898-1903.

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