Phase synchronization circuit

Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By frequency

Reexamination Certificate

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Details

C327S040000

Reexamination Certificate

active

07057419

ABSTRACT:
In a phase sync circuit (40) which extracts a clock signal CK from a data signal D in a random NRZ format, particularly in a phase sync circuit (40) of a dual loop configuration including both a phase comparison circuit (81) and a frequency comparison circuit (10), a phase sync circuit (40) capable of achieving both broadening of the capture range and extraction of a high-quality clock signal without requiring any reference clock signal is provided. A clock signal Ca, another clock signal Cb having a phase delayed by an approximately ¼ period from the clock signal Ca and the data signal D are input to the frequency comparison circuit (10) to output a logical value according to the high-low relationship between the frequency of the clock signal and the bit rate of the data signal D. This logical value is fed back by a frequency comparison loop F2to bring the frequency of the clock signal CK close to the bit rate of the data signal D without requiring any reference clock signal, thus achieving both broadening of the capture range and extraction of a high-quality clock signal.

REFERENCES:
patent: 4547747 (1985-10-01), Wolaver et al.
patent: 5512860 (1996-04-01), Huscroft
patent: 5694088 (1997-12-01), Dickson
patent: 6496555 (2002-12-01), Soda
patent: 6701445 (2004-03-01), Majos
patent: WO 00/13305 (2000-03-01), None

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