Miscellaneous active electrical nonlinear devices – circuits – and – Specific input to output function – Combining of plural signals
Reexamination Certificate
2000-07-07
2001-06-05
Tran, Toan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific input to output function
Combining of plural signals
C327S357000
Reexamination Certificate
active
06242965
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to devices for synchronising an output signal with an input signal, and in particular to devices which use interpolation or mixing of two reference sources to generate the output.
2. The Prior Art
Phase locked loops (PLLs) are well known electronic devices and they function to provide an output oscillating signal which is phase locked with an incoming signal. In most PLL architectures, the output signal is generated by a voltage controlled oscillator (VCO) and this output is compared by a phase detector with the input signal. This produces an error signal representing the phase difference between the input and the output and this error is applied, typically via an appropriate filter, to alter the control voltage of the VCO. The oscillating frequency of the VCO is therefore altered until such time as the output is in base with the input at which time no further error signal is generated and no further changes are made to the control voltage input to the VCO.
PLLs are typically used where it is desired to generate a clean clock signal synchronised with an incoming signal. One particular application of PLLs is in data transmission systems, for instance communication devices where the transmitted signal is modulated based on a signal having a particular frequency and it is important to recover a corresponding clock signal at the receiver in order to demodulate the received signal.
In a typical communication system there may be many PLLs in close proximity. For instance there may be PLLs both in the transmit side of the system and in the receive side, and also in a multi-channel system there may be a PLL for each of the channels. If such arrangements are implemented on a single chip problems can occur due to interference between VCOs implemented in such close proximity. Also as data rates increase, the power consumption of the VCO required to generate a satisfactorily low-noise signal increases and this is compounded if more than one VCO is implemented in any particular device.
It is further known that clock signals may be used in a number of parts of any specific electronic circuitry. In a physical implementation therefore clock signals are cared around a chip or circuit board arrangement by suitable conductive means so as to be transferred from the clock generator to the part of the circuitry dependent on the clock.
SUMMARY OF THE INVENTION
The present invention provides, in a first aspect, apparatus for generating an oscillating output signal having a desired phase relationship with an input signal, comprising:
mixing means arranged to receive first and second reference signals oscillating at a common frequency and having a phase offset between them, and to mix said first and second reference signals in variable proportions to generate said output signals; and
comparing means arranged to compare the phase of said output signal with said input signal and to provide a comparison output signal indicative of whether the phase of said generated output signal is in said desired phase relationship with said input signal;
said mixing means being responsive to said comparison output signal to alter said proportions in which said first and second reference signals are mixed.
In the preferred embodiment the first and second reference signals are in quadrature relationship with each other. In this arrangement good results are achieved when the mixing means is arranged to mix said first and second reference signals in proportions which vary sinusoidally with the required phase difference between the output and one of said first and second reference signals.
In a particularly preferred implementation the mixing proportion for each of said reference signals is represented by a pair of differential weight current signals. These can be used in an arrangement in which said mixing means comprises a plurality of differential amplifiers with each reference signal being applied to two of said differential amplifiers with opposite polarity and current in said two differential amplifiers being supplied respectively by the corresponding pair of differential weight current signals, the sum of the outputs of said differential amplifiers being used to provide said output signal.
The present invention does not therefore require the presence of a voltage controlled oscillator or other clock source implemented as part of a PLL. Rather it depends on the availability of two or more externally generated reference signals, such as may be available elsewhere in the circuitry as mentioned above.
In a stand-alone implementation of a PLL according to this invention, there is thus no requirement for a VCO, as the reference signals can be generated from any suitable oscillatory source. This potentially reduces the power requirements of the PLL.
In an implementation in the context of a communication system as mentioned above, the receiver PLL may be according to this invention and may derive its reference signals from the VCO output in the transmitter side PLL. This removes the possibility of damaging interference between two VCOs on the same chip and also reduces the overall power requirement. Alternatively, both the transmitter and receiver PLLs may receive input clock reference signals from elsewhere.
This invention is particularly suited to situations such as those referred to above in the communications field where the frequency of the desired output is fairly accurately known as in this case the reference signals would be set to have approximately this frequency. However it is possible and potentially useful within the present invention to generate an output signal having a frequency different from the frequency of the reference signals, and therefore synchronise with an input signal of a different frequency.
The comparison between the input and the output signal in the invention is broadly the same as the prior art, that is a signal is generated according to phase comparison between the input and the output signals. In the invention this is used to derive and constantly correct the weightings used in the mixing of the reference signals.
In alternative arrangements, the two references may be arranged non-orthogonal, in which case the relationships between the derived phase relationships and the weighting values is different but can be easily derived. Also it is possible to use three or more references at equal or non-equal phase spacings with appropriate weighting values.
In another aspect the present invention provides apparatus for generating an output pair of quadrature related signals oscillating at a common frequency, having input thereto an input pair of signals oscillating at said frequency and having a phase difference therebetween, comprising:
summing means arranged to sum said two input signals to generate a first signal;
difference means arranged to subtract one of said input signals from the other to generate a second signal; and
output means arranged to generate said output signals from said first and second signals.
Preferably the input signals have a common magnitude, and the magnitudes of said first and second signals are simply equalized in order to provides said output signals.
The quadrature related signals are advantageously used as the reference signals in the PLL, and as will be explained in more detail below a multi-channel communications arrangement can be easily implemented with only one source of clock signals and means arranged to regenerate the quadrature relationship between the clock signals at appropriate points.
REFERENCES:
patent: 5526380 (1996-06-01), Izzard
patent: 6107858 (2000-08-01), Kimura
patent: 0 432 895 (1991-06-01), None
patent: 0 707 379 (1996-04-01), None
patent: 0123456 - A2 (2000-01-01), None
M. J. Izzard et al., “Analog Versus Digital Control of a Clodk Synchronizer for 3GB/S Data With 3.0V Differential ECL” Symposium on VLSI Circuits, US, New York, IEEE, Jun. 9, 1994, pp. 39-40.
T. H. Lee et al., “ISSCC94/Session 18/High-Performance Logic and Circuit Techniques/Paper FA 18.6 A 2.
Joy Andrew Keith
Pickering Andrew James
Simpson Susan Mary
Dykema Gossett PLLC
Nguyen Linh
Phoenix VSLI Consultants Ltd.
Tran Toan
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