Phase shifter for a quadrature modulator and an image...

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Phase shift by less than period of input

Reexamination Certificate

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Details

C327S113000

Reexamination Certificate

active

06181181

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention generally relates to a phase shifter, and, more particularly, to a quadrature modulator and an image suppression mixer each of which includes the phase shifter.
FIG. 1
is a circuit diagram of a conventional phase shifter
11
. The phase shifter
11
comprises a low pass filter (LPF)
12
and a high pass filter (HPF)
13
. The LPF
12
is an integrating circuit including a resistor R
1
and a capacitor C
1
. The HPF
13
is a differential circuit including the capacitor C
2
and the resistor R
2
.
FIG. 2
is a graph showing the relationship between the frequency and phase in the LPF
12
and the HPF
13
. The LPF
12
receives an input signal LOin and generates a first carrier signal LO
1
having a phase of −45 degrees at a cutoff frequency fc. The HPF
13
receives the input signal LOin and generates a second carrier signal LO
2
having a phase of +45 degrees at the cutoff frequency fc. Accordingly, the phase difference between the output signals LO
1
and LO
2
is substantially 90 degrees.
However, the phase shifter
11
of
FIG. 1
is a theoretical circuit, a real circuit therefor being shown in FIG.
3
. The capacitors C
1
, C
2
each has a parasitic resistor Rs. Therefore, the LPF
12
generates a first carrier signal LO
3
having a phase of (−45−&Dgr;) degrees, and the HPF
13
generates a second carrier LO
4
having a phase of (+45+&Dgr;) degrees. Accordingly, the phase difference between the two signals is not exactly 90 degrees. As a result, a circuit for compensating for the phase errors generated by the parasitic resistors Rs is required. This increases the circuit area of the phase shifter
11
.
Another conventional digital phase shifter comprises a frequency divider consisting of a flip-flop. The frequency divider divides the frequency of an input signal in half. The phase shifter generates two output signals in which the phase difference between the signals is substantially 90 degrees using a frequency division signal. However, to divide the frequency of the input signal in half, a frequency multiplier for supplying the input signal in which the frequency is multiplied by two to the frequency divider is required. The provision of the frequency multiplier increases the circuit area of the phase shifter.
A quadrature modulator used in digital mobile communications includes a phase shifter. It is preferable for the quadrature modulator to have a small circuit area and perform modulation with high accuracy. Therefore, a phase shifter having high phase accuracy and small circuit area is necessary.
FIG. 4
is a block diagram of a conventional image suppression mixer circuit (hereinafter referred to as mixer circuit)
211
. The mixer circuit removes an image component contained in the output signal. The mixer circuit
211
includes first and second phase shifters
212
and
213
and an image suppression circuit
214
. The image suppression circuit
214
includes first and second mixers
215
and
216
and a adder
217
.
The first phase shifter
212
receives an intermediate frequency signal IFin and generates first and second intermediate frequency signals IF
0
and IF
90
in which the phase difference between the signals is substantially 90 degrees. The phase difference of the second intermediate frequency signal IF
90
for a first intermediate frequency signal LO
0
is 90 degrees. The second phase shifter
213
receives a local signal LOin having a local oscillation frequency and generates first and second local signals LO
0
and LO-
90
in which the phase difference between the signals is substantially 90 degrees. The phase difference of the second local signal LO-
90
from the first local signal LO
0
is −90 degrees.
The first mixer
215
multiplies the first intermediate frequency signal IF
0
by the first local signal LO
0
and generates a first modulation signal V
1
. The first modulation signal V
1
is obtained in accordance with the following equation (1).
V1
=
cos

(
2

π



f
LO

t
)
×
cos

(
2

π



f
IF

t
)
=
1
2

[
cos

{
2

π

(
f
LO
+
f
IF
)

t
}
+
cos

{
2

π

(
f
LO
-
f
IF
)

t
}
]
The second mixer
216
multiplies the second intermediate frequency signal IF
90
by the second local signal LO-
90
and generates a second modulation signal V
2
. The second modulation signal V
2
is obtained in accordance with the following equation (2).
V2
=
cos

(
2

π



f
LO

t
+
90

°
)
×
cos

(
2

π



f
IF

t
-
90

°
)
=
1
2

[
cos

{
2

π

(
f
LO
+
f
IF
)

t
}
-
cos

{
2

π

(
f
LO
-
f
IF
)

t
}
]
The adder
217
receives the first and second modulation signals V
1
and V
2
from the first and second mixers
215
and
216
and generates an output signal RFout by combining the first and second modulation signals V
1
and V
2
. The output signal RFout is obtained in accordance with the following equation (3).
RFout
=
V1
+
V2
=
cos

{
2

π

(
f
LO
+
f
IF
)

t
}
The output signal RFout includes only the (fL
0
+fIF) component. In Equations (1) and (2), the (fL
0
−fIF) component is an image frequency signal component. Thus, the mixer circuit
11
suppresses or rejects the image frequency component.
The mixer circuit
211
can also be used as a down-converter that reduces the frequency of an input signal. In this case, the first phase shifter
212
receives a high frequency input signal RFin that is a receiving signal for communication devices. The mixer circuit
211
combines the input signal RFin and the local signal LOin having the local oscillation frequency and generates an output signal IFout having an intermediate frequency that is lower than that of the input signal RFin. The output signal IFout is obtained in accordance with the following equation (4).
IFout=V
1
+V
2
=cos{2&pgr;(f
L0
+f
IF
)
t}
The mixer circuit
211
implements highly accurate image suppression by accurately maintaining the phase difference among the output signals IF
0
, IF
90
, LO
0
, and LO-
90
of the first and second phase shifters
212
and
213
at 90 degrees. However, if the phase shifters
212
and
213
are not manufactured evenly, the phase difference of the output signal is not accurately maintained at 90 degrees. This makes it difficult to fully suppress the image frequency component.
To solve the aforementioned problems, Japanese Unexamined Patent Publication No. 8-125447 discloses an improved image suppression mixer circuit. The image suppression mixer circuit comprises two unit mixers that output direct current (DC) signals and a comparator that receives the DC signals output from the two unit mixers via a variable phase shifter and a phase shifter and calculates the phase difference of the first and second IF signals based on the level difference of the DC signals. The image suppression mixer circuit further includes a driver that controls the variable shifter so that a phase error is zero. Thus, a relative phase error is corrected and an image frequency component is suppressed. However, because the variable phase shifter is connected to the input of a adder, the mixer circuit is used only for the application of down-conversion. Further, the mixer circuit includes a coupler. Neither the mixer nor the coupler is integrated on a semiconductor substrate. This impedes miniaturization of the mixer circuit.
It is an object of the present invention to provide a phase shifter that obtains the two output signals in which the phase difference between the signals is substantially 90 degrees and has a small circuit area.
It is the second object of the present invention to provide an image suppression mixer that reduces differences due to uneven manufacturing.
SUMMARY OF THE INVENTION
Briefly stated, the present invention provides a phase shifter. The phase shifter includes a low pass filter for receiving an input signal

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