Wave transmission lines and networks – Coupling networks – Delay lines including long line elements
Reexamination Certificate
2002-08-27
2004-01-06
Young, Brian (Department: 2816)
Wave transmission lines and networks
Coupling networks
Delay lines including long line elements
C333S139000, C333S138000, C333S08100R
Reexamination Certificate
active
06674341
ABSTRACT:
TECHNICAL FIELD
This invention relates to a phase shifter and a multi-bit phase shifter electrically changing pass phase of a signal in microwave and extremely high frequency band.
BACKGROUND ART
A conventional phase shifter is shown in
FIG. 11
, for example one described in Joseph F. White “Microwave Semiconductor Application Engineering” (CQ Publishing, pp. 336-339).
In
FIG. 11
, input/output terminals
1
a
,
1
b
, single-pole double-throw (SPDT) switches
9
a
,
9
b
, and transmission lines
10
a
,
10
b
are shown.
The phase shifter shown in
FIG. 11
operates as follows.
Radio frequency (RF) signal input from an input/output terminal
1
a
is switched by a SPDT switch
9
a.
A case where the RF signal passes through a transmission line
10
a
is described below. The RF signal switched by the SPDT switch
9
a
is input to a SPDT switch
9
b
through the transmission line
10
a
. The SPDT switch
9
b
operates cooperatively with the SPDT switch
9
a
, and the RF signal is output from an input/output terminal
1
b.
Next, a case where the RF signal passes through a transmission line
10
b
is described below. The RF signal switched by the SPDT switch
9
a
is input to a SPDT switch
9
b
through the transmission line
10
b
. The SPDT switch
9
b
operates cooperatively with the SPDT switch
9
a
, and the RF signal is output from the input/output terminal
1
b.
In the phase shifter, the length of the transmission line
10
a
is different from the length of the transmission line
10
b
, and the pass phase can be switched depending on whether the RF signal passes through the transmission line
10
a
or
10
b.
The conventional phase shifter has a problem of increased circuit size because the transmission lines with different lengths are used depending on the magnitude of phase shift.
Therefore, it is an object of the invention to overcome the above problem and provide a miniaturized phase shifter and multi-bit phase shifter in which a filter is constructed from a capacitor at FET pinch-off and pass phase can be changed by turning the FET on and off.
DISCLOSURE OF THE INVENTION
In order to attain the above-mentioned object, a phase shifter according to the present invention comprises: a first FET having a drain electrode connected to an input terminal and a source electrode connected to an output terminal; a second FET, in which one of a drain electrode and a source electrode thereof is connected to the source electrode of the first FET, and the other is connected to ground via a first inductor; and a third FET, in which one of a drain electrode and a source electrode thereof is connected to the drain electrode of the first FET, and the other is connected to ground via a second inductor.
Also, the phase shifter is characterized in that the first inductor is connected between the drain electrode and the source electrode of the second FET, and the second inductor is connected between the drain electrode and the source electrode of the third FET.
Also, the phase shifter is characterized in that a first capacitor is connected between the drain electrode and the source electrode of the first FET.
Also, the phase shifter is characterized in that a first capacitor is connected between the drain electrode and the source electrode of the second FET, and a second capacitor is connected between the drain electrode and the source electrode of the third FET.
Also, the phase shifter is characterized in that the drain electrode of the first FET is connected in common to one of the drain electrode and the source electrode of the second FET, and the source electrode of the first FET is connected in common to one of the drain electrode and the source electrode of the third FET.
Further, a multi-bit phase shifter according to the present invention includes a combination of a plurality of phase shifters each having different magnitudes of phase shift, the phase shifter comprising: a first FET having a drain electrode connected to an input terminal and a source electrode connected to an output terminal; a second FET, in which one of a drain electrode and a source electrode thereof is connected to the source electrode of the first FET, and the other is connected to ground via a first inductor; and a third FET, in which one of a drain electrode and a source electrode thereof is connected to the drain electrode of the first FET, and the other is connected to ground via a second inductor.
Also, the multi-bit phase shifter is characterized in that a third inductor is connected between the drain electrode and the source electrode of the second FET, and a fourth inductor is connected between the drain electrode and the source electrode of the third FET.
Also, the multi-bit phase shifter is characterized by further comprising a 180-degree bit phase shifter constituted by a switching phase shifter in which a low pass filter and a high pass filter are switched by a single-pole double-throw (SPDT) switch, characterized in that a phase shifter having the first through the third FETs and the first through the fourth inductors is used as a 90-degree bit phase shifter.
Also, the multi-bit phase shifter is characterized by further comprising: a 45-degree bit phase shifter having the same configuration as the 90-degree bit phase shifter; a 22.5-degree bit phase shifter wherein a fifth inductor is connected in parallel between a drain and a source of a fourth FET, a sixth inductor with one end thereof being connected to ground is connected to one of a drain and a source of a fifth FET by means of a switch, and the drain and source of the fifth FET are used as an input terminal and an output terminal, respectively; and a 11.25-degree bit phase shifter wherein a seventh inductor is connected in parallel between a drain and a source of a sixth FET, and the drain and source of the sixth FET are used as an input terminal and an output terminal, respectively.
Also, the multi-bit phase shifter is characterized in that a first capacitor is connected between the drain electrode and the source electrode of the first FET.
Also, the multi-bit phase shifter is characterized in that a first capacitor is connected between the drain electrode and the source electrode of the second FET, and a second capacitor is connected between the drain electrode and the source electrode of the third FET.
Also, the multi-bit phase shifter is characterized in that the drain electrode of the first FET is connected in common with one of the drain electrode and the source electrode of the second FET, and the source electrode of the first FET is connected in common with one of the drain electrode and the source electrode of the third FET.
REFERENCES:
patent: 5502421 (1996-03-01), Nakahara
patent: 5519349 (1996-05-01), Nakahara
patent: 5701107 (1997-12-01), Kasahara et al.
patent: 6252474 (2001-06-01), Mizutani
patent: 6275121 (2001-08-01), Sasaki et al.
patent: 1-202007 (1989-08-01), None
patent: 3-204218 (1991-09-01), None
Campbell et al., IEEE MIT-s, International Microwave Symposium Digest, pp. 217-220 (2000).
Joseph F. White, Microwave Semiconductor Application Engineering, First Edition (1985).
Hieda Morishige
Ikematsu Hiroshi
Inami Kazuyoshi
Kasahara Michiaki
Miyaguchi Kenichi
Mitsubishi Denki & Kabushiki Kaisha
Nguyen John
Young Brian
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