Phase-shift calculation method, and system implementing it,...

Details Phase-shift calculation method, and system implementing it,... Phase-shift calculation method, and system implementing it,...

1999-02-26

2002-08-27

Chin, Stephen (Department: 2734)

Pulse or digital communications

Equalizers

C375S232000, C375S233000, C375S231000

Reexamination Certificate

active

06442197

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method for estimating the total phase error at a finite-impulse-response (FIR) filter's output by observing the input data, assuming the coefficients of the FIR filter are ascertained a priori. The coefficients may be ascertained either by programming them in memory or by adapting them via a least mean squares method (LMS).
BACKGROUND
A FIR filter may be included in the general class of devices referred to as digital signal processors (DSP). This does not mean that the FIR can operate only on digital signals, however.
A “digital signal” is a signal that conveys a discrete number of values at discrete times. Contrast the “analog signal,” i.e., a signal that conveys an infinite number of values whether continuous time or discrete time. A signal having a digital form may be generated from an analog signal through sampling and quantizing the analog signal. Sampling an analog signal refers to “chopping” the signal into discrete time periods and capturing an amplitude value from the signal in selected ones of those periods. The captured value becomes the value of the digital signal during that sample period. Such a captured value is referred to as a sample.
Quantizing refers to approximating a sample with a value that may be represented on a like digital signal. For example, a sample may lie between two values characterized upon the digital signal. The value nearest (in absolute value) to the sample may be used to represent the sample.
Alternatively, the sample may be represented by the lower of the two values between which the sample lies. After quantization, a sample from an analog signal may be conveyed as a digital signal. This is the resultant signal upon which the FIR filter may operate.
A DSP transforms an input digital signal to an output digital signal. For the digital FIR filter, the transformation involves filtering out undesired portions of the received digital signal. An original analog signal may be represented as a sum of a plurality of sinusoids. Each sinusoid oscillates at a particular and unique frequency. Filtering is used to remove certain frequencies from an input signal while leaving other frequencies intact.
A FIR filter is a device in which an input sample produces a finite number of output samples. After the finite number of samples expires, the FIR filter output is no longer affected by that particular input sample. Transversal filters, of which FIR filters may be a class, are filters in which a certain number of past samples are used along with the current sample to create each output sample.
Programs executing on FIR filters often do so in “real-time.” Real-time programs are programs that must execute within a certain time interval. Regardless of whether a program executes in a large period of time or a small period of time, the result of executing the program is the same. However, if real-time programs attempt to execute in an amount of time longer than the required time interval, then they no longer will compute the desired result.
Programs executing on a FIR filter are real-time programs in that the instructions are manipulating a sample of a digital signal during the interval preceding the receipt of the next sample. If the program cannot complete manipulating a sample before the next sample is provided, then the program will eventually begin to “lose” samples. A lost sample does not get processed, and therefore the output signal of the FIR filter no longer contains all of the information from the input signal provided to the FIR filter. This potential for losing samples is reduced by a preferred embodiment of the present invention, while maintaining a required throughput rate.
A FIR filter may be programmed to modify signals. The number of instructions required to do this is relatively fixed. A FIR filter must be capable of executing this relatively fixed number of instructions on any given sample before the next sample of the series is provided.
A typical example of a high-speed FIR with five or more coefficients is a Type II FIR. A Type II FIR is based on an array of costly Multiply and Add (MAC) accumulation stages. A conventional system using MAC is constrained to a minimum number of gates to achieve a given partial product accuracy. Digital implementation of an FIR filter is also limited by the maximum number of logic gates that can be inserted between reclocking stages established by the filter's clock cycle. Thus, for a given digital process, a minimum time to process is established by the propagation time through the critical path. To achieve very high speeds of processing, the critical path is broken into a number of shorter paths that can be addressed at higher clock speeds, i.e., processed within a short clock cycle.
Some conventional high-speed systems employing FIR filters use an analog FIR filter placed before an analog-to-digital converter (ADC). This prevents the FIR filter's latency from accumulating in the sampled timing recovery loop. This method is inherently not well suited to digitally intensive designs.
Some existing designs always include the FIR filter in the timing recovery loop, increasing latency ab initio, and decreasing stability of the embedded loops, both the timing recovery and gain loops, for example.
The time it takes a timing recovery loop to synchronize to a reference impacts both speed of acquisition and “geography” that must be devoted to this function, e.g., disk space on the disk drive of a recorder. Conventionally, when READ mode is entered on the disk drive, a PLL acquires the initial clock frequency (i.e., natural data frequency) of the incoming signal from a sinusoidal preamble. A key parameter to optimize is the timing recovery &Dgr;t, or time to recover, associated with acquiring phase and timing from this preamble. The amount of disk space assigned to this activity needs to be minimized.
Other designs bypass the FIR filter during acquisition mode but require the coefficients of the FIR filter to be symmetric in order to avoid a phase hit when switching back the FIR filter at the end of the acquisition mode.
The dynamic power dissipated in conventional filter circuit implementations (assuming the use of CMOS ICs) is given by the relationship:
P∝C×V
2
׃×N
Gate
  (1)
where:
C =
the average loading capacitance of a gate in the IC chip,
V =
the power supply voltage level,
f =
the operating frequency, and
N
gate =
the number of gates that are switching at frequency, f.
Improved performance is generally realized with a higher operating frequency,ƒ, but comes at the expense of higher power dissipation levels. From Eqn. (2), power consumption also increases in proportion to the number of gates. A common IC embodiment of FIR filters is a tapped delay line, in which each of the coefficients characterizing the filter corresponds to a separate “tap” along a delay line. The number of gates goes up in proportion to the number of taps. The number of taps dictates the overall time delay for data (in Type I FIR structure) to pass through the filter and thus limits the operating frequency (data rate). To compensate for this delay, data pipelining is introduced to increase the FIR filter's operating frequency and the effective system throughput. However, pipelining calls for more gates, resulting in even greater power consumption.
In magneto-resistive (MR) heads using FIR filters, with the MR head's inherent response nonlinearities, this constraint is becoming even more unacceptable. There are more modem methods that achieve a fully digital solution, but these are extremely complex while covering a disproportionately large area on a silicon chip. In one design, discrete time analog values are entered in memory as are weights, some of which are set to zero to improve throughput. In this architecture neither pass through delay lines.
In a magnetic disk data storage system, for example, information is recorded by inducing a pattern of magnetic variations on the disk, thus

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