Phase selector for external frequency divider and phase locked l

Oscillators – Automatic frequency stabilization using a phase or frequency... – Afc with logic elements

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331 25, 331 45, 331 74, 331DIG2, 327115, 327142, 327147, 327295, H03L 706, H03L 716, H03K 2138

Patent

active

059778377

ABSTRACT:
A method for removing an external frequency divider and clock formation circuit from a feedback path of a phase locked loop and a phase selector circuit are provided for synchronizing an external frequency divider with a reference clock of a phase locked loop. A reference clock signal is applied to the phase locked loop. An output of the phase locked loop is coupled through a predefined delay and provides a delayed feedback clock signal input to the phase locked loop. The external frequency divider is located at the output of the phase locked loop external to the predefined delay and outside the feedback clock signal path of the phase locked loop. A phase selector circuit identifies a correct phase of the reference clock signal and starts the external frequency divider. The phase selector circuit includes an edge detector, a synchronization divider, and a reset machine.

REFERENCES:
patent: 4206425 (1980-06-01), Nossen
patent: 4360788 (1982-11-01), Erps et al.
patent: 4600895 (1986-07-01), Landsman
patent: 4999526 (1991-03-01), Dudley
patent: 5124572 (1992-06-01), Mason et al.
patent: 5517147 (1996-05-01), Burroughs et al.
patent: 5557224 (1996-09-01), Wright et al.

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