Phase selection mechanism for optimal sampling of source...

Details Phase selection mechanism for optimal sampling of source... Phase selection mechanism for optimal sampling of source...

2006-01-24

2006-01-24

Chin, Stephen (Department: 2634)

Pulse or digital communications

Synchronizers

Synchronizing the sampling time of digital data

C327S144000

Reexamination Certificate

active

06990161

ABSTRACT:
Phase selection mechanisms for the optimal sampling of data at the receiving end of a SSC interface. The receiver is allowed to choose between several phases of its local clock, to best synchronize the transmitter data to the receiver clock domain. It results in a minimum depth first in first out (FIFO) register to accomplish the handoff of transmit data from the transmit clock to the receive dock. It avoids the requirement of a delay locked loop (DLL) to bring the transmitter clock into a desired phase relationship with respect to the receiver clock. At least one embodiment of the present invention provides a solution specific to the DDR or full rate clocking SSC interface.

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D.J. Friedman et al., “A Single-Chip 12.5Gbaud Transceiver for Serial Data Communication”, 2001 Symposium on VLSI Circuits, Kyoto, Japan, Jun. 2001.

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