Phase-selectable flip-flop

Details Phase-selectable flip-flop Phase-selectable flip-flop

1987-09-18

1991-04-02

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

3072721, 307236, 307262, 328 72, H03K 5135

Patent

active

050049330

ABSTRACT:
A phase-selectable flip-flop has an input dual-enable transparent latch and an output D-type flip-flop. A clock is input to one enable of the transparent latch and to the flip-flop, and a command is input to the second enable of the transparent latch. When the command is in a first state the latch is held transparent and data is clocked into the flip-flop on the rising edge of the clock, and when the command is in a second state data is held by the transparent latch on the falling edge of the clock and clocked into the flip-flop on the succeeding rising edge.

REFERENCES:
patent: 4039960 (1977-08-01), Clark
patent: 4080576 (1978-03-01), Huber et al.
patent: 4334157 (1982-06-01), Ferris
patent: 4620180 (1986-10-01), Carlton
patent: 4627085 (1986-12-01), Yuen
patent: 4629909 (1986-12-01), Cameron
patent: 4633487 (1986-12-01), Goeb et al.
J. W. Cannon, "Phase Selector and Synchronizer for Two-Phase Clock Circuits", vol. 25, No. 11A, Apr. 1983--IBM Technical Disclosure Bulletin.
H. P. Muhfeld, "Trapeze Latch", IBM Technical Disclosure Bulletin, vol. 21, No. 1--Jun. 1978.
T. W. Williams, "Single Clock Shift Register Latch", IBM Technical Bulletin Disclosure--vol. 16, No. 6--Nov. 1973.

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