Phase register for synchronization of multiple signal processors

Details Phase register for synchronization of multiple signal processors Phase register for synchronization of multiple signal processors

1995-12-06

1996-12-03

Kriess, Kevin A.

Pulse or digital communications

Repeaters

Testing

375357, 375363, 375368, 395551, H04L 708, H04J 306

Patent

active

055817483

ABSTRACT:
In a computer system having two processors both of which are used to process frames, a method for synchronizing a first set of frames corresponding to the first processor with a second set of frames corresponding to the second processor. A value stored in a register is initialized at frame boundaries of the second set of frames. This register value is repeatedly incremented during the frames of the second set of frames so that it increases within the frames. The value in the register is read. A timer value which provides a timing reference for each frame of the first set of frames is read. The value stored in the register when a frame boundary of the second set of frames had occurred is computed, based on the read register value and the read timing value. Based on the computed values, a frame length of the first set of frames is adjusted to maintain or improve frame synchronization between the two frame sets. Furthermore, data synchronization is provided in a similar fashion.

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