Phase noise reduction circuits

Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – Unwanted signal suppression

Reexamination Certificate

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Details

C327S113000

Reexamination Certificate

active

06275101

ABSTRACT:

This invention relates to phase noise reduction circuits.
The output from a frequency source, such as an oscillator or a frequency synthesiser will always contain phase noise which may be in the form of broadband noise or discrete component noise. Phase noise is undesirable in that it may ultimately limit the performance of any system (e.g. a communications or radar system) containing the frequency source. Accordingly, a low phase noise frequency source will frequently incorporate some form of compensation circuit which is designed to limit the extent of any phase noise that may be produced. However, a compensation circuit has the disadvantage that it adds to the overall complexity and expense of the frequency source.
By way of illustration, EP-A-0089721 describes a variable frequency synthesiser including a phase lock loop and a compensation circuit which is connected to the loop to reduce phase jitter therein. The compensation circuit includes an integrator and a phase modulator. The output from the integrator represents the amount of phase noise in the phase lock loop, and this output is used to control the phase modulator. The phase modulator responds to the integrator output by adjusting the relative phases of reference pulses supplied to the phase lock loop to reduce the amount of phase noise present.
According to a first aspect of the invention there is provided a phase noise reduction circuit for reducing phase noise in an input pulse train consisting of pulses which are all of the same length and which, in the absence of phase noise, have a nominal frequency f, the phase noise reduction circuit including DC removal means for removing a DC level from the input pulse train, integrator means for integrating the input pulse train after a DC level has been removed therefrom by the DC removal means, and processing means for deriving from the integrated pulse train an output pulse train containing periodic transitions at said nominal frequency.
According to a second aspect of the invention there is provided a phase noise reduction circuit for reducing phase noise contained in an input pulse train produced by a frequency source, which pulse train, in the absence of any phase noise, has a nominal frequency f, the phase noise reduction circuit comprising, pulse generating means for deriving a modified pulse train from the Input pulse train, the modified pulse train consisting of pulses which all of the same length and are all triggered by the positive-going (or alternatively the negative-going) transitions of the pulses forming the input pulse train, and compensation means including, DC removal means for removing a DC level from the modified pulse train, integration means for integrating the modified pulse train after a DC level has been removed therefrom by the DC removal means and processing means for deriving from the integrated pulse train an output pulse train containing periodic transitions at said nominal frequency.
According to a third aspect of the invention there is provided a phase noise reduction circuit for reducing phase noise contained in an input pulse train produced by a frequency source, which pulse train in the absence of any phase noise has a nominal frequency, f, the phase noise reduction circuit comprising a first pulse generating means for deriving a first modified pulse train from the input pulse train, the first modified pulse train consisting of pulses which are all of the same length and are triggered by the positive-going transitions of the pulses forming the input pulse train, a second pulse generating means for deriving a second modified pulse train from the input pulse train, the second modified pulse train consisting of pulses which are all of the same length and are triggered by the negative-going transitions of the pulses forming the input pulse train, first compensation means including first DC removal means for removing a DC level from the first modified pulse train, first integrator means for integrating the first modified pulse train after a DC level has been removed therefrom by the first DC removal means and first processing means for deriving from the integrated pulse train output by the first integrator means a first output pulse train containing transitions which are periodic and have the frequency, second compensation means including second DC removal means for removing a DC level from the second modified pulse train, second integrator means for integrating the second modified pulse train after a DC level has been removed therefrom by the second DC removal means and second processing means for deriving from the integrated pulse train output by the second integrator means a second output pulse train also containing transitions which are periodic and have the frequency, first and second output circuits for extracting from the first and second pulse trains respectively first and second periodic pulse trains respectively, and combining means for combining the first and second periodic pulse trains to produce a combined output pulse train at said nominal frequency f.
It will be appreciated that phase noise reduction circuits according to the invention have the capability to operate on the pulse train produced at the output of a frequency source, and need not form a part of the frequency source itself.


REFERENCES:
patent: 4137504 (1979-01-01), Simmons
patent: 4599579 (1986-07-01), McCann
patent: 4602219 (1986-07-01), Underhill et al.
patent: 4746870 (1988-05-01), Underhill
patent: 4780888 (1988-10-01), Solhjell et al.
patent: 5245557 (1993-09-01), Upton
patent: 0089721 (1983-09-01), None
patent: 0229265 (1987-07-01), None
patent: 2578367 (1986-09-01), None
patent: 2117197 (1983-10-01), None
Japio Abstract of Japanese Patent JP 7264011.
Japio Abstract of Japanese Patent JP. 4048823.
Japio Abstract of Japanese Patent JP 57207419.
Inspec Abstract of Non-Patent Journal “Continuous Phase Shifter for Square Waves” by Rama Murthy, TV in Journal “Electronic Engineering” vol. 51, No. 621, p19, Apr. 1979. UK

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