Phase logic

Details Phase logic Phase logic

1974-03-13

1976-01-27

Miller, Jr., Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307214, 307215, 307221C, 307224C, H03K 1908, H03K 1936, H03K 1940, G11C 1928

Patent

active

039354741

ABSTRACT:
In a logic cell, a plurality of gates are serially connected and responsive to signals on a plurality of conductors to perform a particular logic function. The gates are responsive to subsystem clock signals which control the operation of the gates to delay the output of the logic cell. The cell includes at least one ratioless gate, and at least one ratioed gate. The ratioless gates provide high speed and reduced size, while the ratioed gates provide low noise characteristics. In combination, the ratioed gates, which provide strong output signals, make excellent drivers for the ratioless gates which are particularly adapted to accommodate complex logic networks.

REFERENCES:
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patent: 3518451 (1970-06-01), Booher
patent: 3524077 (1970-08-01), Kaufman
patent: 3526783 (1970-09-01), Booher
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patent: 3588528 (1971-06-01), Terman
patent: 3617767 (1971-11-01), Booher
patent: 3638036 (1972-01-01), Zimbelmann
patent: 3648066 (1972-03-01), Terman
patent: 3651334 (1972-03-01), Thompson et al.
patent: 3747064 (1973-07-01), Thompson
Long, "Dynamic Logic Circuit Family", IBM Tech. Discl. Bull., Vol. 16, No. 5, pp. 1560, 10/1973.
West, Practical Circuit Design Using M.D.S., Design Electronics (pub.), pp. 30-32,37,38, 3/1971.
Yao, "Dynamic Shift Register Cyclic Encoder", IBM Tech. Discl. Bull., Vol. 12, No. 11, pp. 1936-1938, 4/1970.

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