Phase locking circuit for jitter reduction in a digital multiple

Details Phase locking circuit for jitter reduction in a digital multiple Phase locking circuit for jitter reduction in a digital multiple

1993-09-29

1995-03-28

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

331 17, 375372, 375376, H04J 306

Patent

active

054024250

ABSTRACT:
A digital multiplex system has a buffer, to which a bitstream arrives at one frequency and from which a bitstream is forwarded at a different frequency. The output bitstream frequency is controlled by a phase locking circuit comprising a phase comparator, a voltage controlled oscillator and a control circuit. The buffer generates control signals indicating the phase of the pulses in the incoming bitstream and the phase of the pulses forwarded therefrom. The phase comparator receives said control signals and delivers a signal representative of the mutual phase position of the pulses in the incoming and the forwarded bitstream, the signal being fed to the control circuit for automatic gain control. The control circuit controls the pulse rate of the voltage controlled oscillator, which generates clock pulses for clocking the pulses of the forwarded bitstream. The control circuit comprises a feed-back operational amplifier. Two anti-parallel coupled diode are arranged on one input of the amplifier for achieving automatic gain control, the other input of the amplifier being connected to a reference voltage.

REFERENCES:
patent: 4129748 (1978-12-01), Saylor
patent: 4580100 (1986-04-01), Suzuki et al.
patent: 4704722 (1987-11-01), Henry
patent: 4952887 (1990-08-01), Ashley
patent: 5184350 (1993-02-01), Dara
patent: 5200982 (1993-04-01), Weeber
patent: 5245636 (1993-09-01), Sari et al.
patent: 5267267 (1993-11-01), Kazawa et al.

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