Phase locked system for generating distributed clocks

Details Phase locked system for generating distributed clocks Phase locked system for generating distributed clocks

2008-05-20

2008-05-20

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S159000

Reexamination Certificate

active

07375562

ABSTRACT:
A PLL apparatus and system for generating distributed clocks are disclosed. A synchronizing-edge detector is provided to the PLL apparatus in the PLL system to detect synchronizing edges of the input and output clock signals having gear relationship for the PLL apparatus. The synchronizing-edge detector detects a sample signal the frequency of which is the common divisor of the frequencies of the input and output signal. The PLL apparatus may be provided with a detection terminal connected with one of the input terminals of a pre-divider and loop divider for outputting the sample signal. Alternatively, the PLL system can comprise at least one additional divider coupled to the input and/or output signals of a PLL apparatus to generate the sample signal.

REFERENCES:
patent: 4791488 (1988-12-01), Fukazawa et al.
patent: 5304954 (1994-04-01), Saito et al.
patent: 6386512 (2002-05-01), Pecot et al.
patent: 7154344 (2006-12-01), Thies et al.
patent: 2003/0060177 (2003-03-01), Noboru et al.
patent: 2005/0275473 (2005-12-01), Thies et al.

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