Television – Synchronization – Sync separation
Utility Patent
1994-04-01
2001-01-02
Harvey, David E. (Department: 2714)
Television
Synchronization
Sync separation
C348S637000
Utility Patent
active
06169581
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to video signal processing and more particularly to a method and apparatus for stripping synchronization information from a composite video signal.
2. Background Art
A composite video signal contains synchronization (sync) information encoded on it. A display processor uses sync to create a phased lock pixel clock. This allows the display processor to generate synthetic symbols. The sync format may be any one of several different compositions, however, in many circumstances the output sync format must not change regardless of the input format. To accomplish this desired output, the display processor must strip sync off without affecting the rest of the video signal.
Most prior art sync strippers generally comprise up to four matched diodes or transistors which require the video to be properly dc biased. Circuits of this type generally have associated high impedances which require buffering into and out of the circuit. The prior art devices are also temperature sensitive, which require complex temperature compensating networks.
U.S. Pat. No. 5,140,422 to Constable is a prior art solution to removing sync from the composite video signal. There are several problems with the Constable implementation. The National Television Standards Committee (NTSC) (composite) video signal must be delayed with respect to the N_SYNC signal which is created by the NTSC video. A delay circuit is damaging to the quality of the video. Delay circuits have low pass filter characteristics; that is, they are band limiting so high frequency components, such as edges and lines, etc., will become fuzzy or disappear completely. Delay circuits also add in noise and generally are not usable over temperature extremes.
Furthermore, Constable as disclosed will not work. The control signal N_SYNC preferably goes high slightly after the video sync interval has ended. Therefore, the signal must be delayed with respect to itself then the signal must be made to last longer. The delay circuit is disclosed but Constable fails to teach how the signal can be made to last longer.
U.S. Pat. No. 4,379,309 to Berke et al. describes the matched diode or transistor embodiment as described above. The circuit is a very complex non-linear circuit that is not stable over temperature, or production lots of transistors or diodes. This circuit is an amplitude limiter which has all the problems of an amplitude system, which include temperature compensation, non-linearity and parasitic problems.
U.S. Pat. No. 4,464,679 to Wargo describes using a phase-locked loop (PLL) and composite sync to hook up to a microprocessor interface for a video system. Wargo teaches detecting sync and does not disclose sync stripping.
U.S. Pat. No. 5,189,515 to Chen describes the use of a PLL to eliminate equalization pulses and noise from the composite sync signal after the sync signal has been detected. Chen discloses a PLL to generate horizontal and vertical sync signals using digital techniques by separating the horizontal and vertical signals from the composite sync signals. Chen does not teach using the PLL to strip the composite sync signal off the composite video signal.
Delay lines are used in the prior art to make the current pulse width completely blank the composite sync. A signal of any width occurring anywhere with respect to the sync is disclosed by using a PLL. As a result of using the PLL instead of delay lines, a much higher quality, high bandwidth video can be processed. Additionally, contrary to the prior art devices, the present invention is temperature independent.
SUMMARY OF THE INVENTION
In accordance with the present invention there is provided an apparatus and method for stripping the synchronization (sync) component from a composite video signal. The preferred circuit for stripping a sync component from a composite video signal comprises a phase-locked loop (PLL) for creating a high frequency clock, phase-locked with a video sync signal, and for generating a signal that encompasses the video sync signal, and an analog switch controlled by the signal that encompasses the video sync signal for stripping the video sync signal from the composite video signal.
The preferred PLL comprises a circuit for determining a leading edge of the video sync signal. An alternative embodiment of the PLL comprises a circuit for determining a trailing edge of the video sync signal.
The preferred signal that encompasses the video sync signal comprises a circuit for starting the signal at a first time period prior to the video sync signal and ending the signal at a second time period after the video sync signal. The preferred embodiment comprises a circuit for making the time periods selectable. The preferred time periods are longer than an activation time for the analog switch.
The signal that encompasses the video sync signal further comprises an analog switch activation time. The preferred time periods are also longer than
1
frequency
of the high frequency clock.
The preferred analog switch comprises a switchable input operational amplifier. The analog switch can also comprise an analog multiplier.
The preferred analog switch comprises a circuit for switching a blank level voltage onto the composite video signal. The analog switch alternatively comprises a circuit for stripping horizontal sync. The analog switch can also comprise a circuit for stripping vertical sync.
The preferred circuit for stripping a synchronization component from a composite video signal comprises a phase-locked loop comprising a 10 MHz clock phase-locked with a leading edge of a video sync signal, and a signal that encompasses the video sync signal comprising a circuit for starting the signal, 1 clock oscillation before a leading edge of the video sync and ending at approximately 50 clock oscillations thereafter, and an analog switch comprising a switchable input operational amplifier controlled by the signal, for switching a blank level voltage onto the composite video signal.
The preferred method of stripping a synchronization component from a composite video signal comprises the steps of creating a high frequency clock, phase-locked with a video sync signal and for generating a signal that encompasses the video sync signal, controlling the signal that encompasses the video sync signal with an analog switch, and stripping the video sync signal from the composite video signal with the analog switch.
The preferred step of creating comprises determining a leading edge of the video sync signal. The alternative step of creating comprises determining a trailing edge of the video sync signal.
The preferred step of generating comprises starting the signal that encompasses the video sync signal at a first time period prior to the video sync signal and ending the signal that encompasses the video sync signal at a second time period after the video sync signal. An alternative embodiment comprises selecting the time periods.
The preferred step of generating a signal that encompasses the video sync signal comprises selecting time periods that are longer than a time for the analog switch to activate. The preferred step of generating a signal that encompasses the video sync signal further comprises determining an analog switch activation time.
The preferred step of selecting time periods comprises providing a time period longer than
1
frequency
of the high frequency clock.
The preferred step of providing an analog switch comprises providing a switchable input operational amplifier. The alternative step of providing an analog switch comprises providing an analog multiplier. The preferred step of providing an analog switch comprises switching a blank level voltage onto the composite video signal. The alternative step of providing an analog switch comprises stripping horizontal sync. Another alternative step of providing an analog switch comprises stripping vertical sync.
A primary object of the present invention is to provide a sync stripper without matched diodes or transistors.
Another object of the present inven
Abeyta Andrew A.
Harvey David E.
Honeywell Inc.
Yeadon Loria B.
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