Phase locked loops including analog multiplier networks that...

Details Phase locked loops including analog multiplier networks that... Phase locked loops including analog multiplier networks that...

2000-09-27

2002-03-05

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S159000, C331S017000, C331S025000

Reexamination Certificate

active

06353348

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to electronic circuits, and more particularly to phase locked loops.
BACKGROUND OF THE INVENTION
Phase locked loops are widely used in electronic systems. For example, phase locked loops are widely used in communications systems, including but not limited to radio frequency communications systems such as radiotelephones.
FIG. 1
is a block diagram illustrating a conventional phase locked loop.
Referring now to
FIG. 1
, a conventional phase locked loop
100
includes a controlled oscillator
102
, such as a Voltage Controlled Oscillator (VCO) that is responsive to a control signal
104
, to generate an output signal
106
, the frequency of which is a function of the control signal. A sinusoidal phase detector
108
, also referred to as a multiplier or phase comparator, is responsive to a reference frequency input signal
112
that may be provided by a reference oscillator
124
. The phase detector
108
is also responsive to a divided output signal
122
that is produced by passing the output signal
106
through a divider
120
that divides the output signal
106
by a number
118
, referred to as “N”. The phase detector produces an error signal
114
. A loop filter
116
filters the error signal
114
, to thereby produce the control signal
104
that is provided to the voltage controlled oscillator
102
. The design and operation of phase locked loops
100
and the individual components thereof are well known to those having skill in the art and need not be described further herein.
As the performance of electronic systems continues to improve, it may be desirable to obtain improved performance from the phase locked loop. For example, in radiotelephone communications systems, some coverage areas may be sparsely populated and may have a relatively flat geographical terrain. These areas may be covered by a wide-area coverage system, where the coverage area can be very large. A wide-area system can cover the geographical area with fewer base station sites, and can thus result in a more economical solution for implementing a radiotelephone system. In such wide area coverage systems, it may be important to have a low system noise figure, so that weaker signals can be received. In these applications, the phase locked loop noise may be a limiting factor in determining the system noise figure.
Accordingly, in many applications of phase locked loops, it may be important to lower the phase locked loop noise. More specifically, in many systems, the performance of the phase locked loop may determine the overall system performance. Phase noise performance, spurious performance and frequency settling time are three performance characteristics of a phase locked loop that can be improved and that can be significant in determining overall system performance.
As is well known to those having skill in the art, a phase locked loop includes a parameter referred to as loop bandwidth (&ohgr;
0
) that can greatly impact the phase noise performance, spurious performance and frequency settling time. Accordingly, the loop bandwidth may be a critical parameter within the phase locked loop that can impact phase locked loop performance and therefore impact overall system performance.
In the design of the phase locked loop, the loop bandwidth may be generally assumed to be constant. However, in actual embodiments of phase locked loops, the loop bandwidth may not be a constant as a function of frequency. Accordingly, in order to improve the performance of a phase locked loop, it may be desirable to provide a phase locked loop that has a constant looped bandwidth as a function of frequency.
One attempt at providing a phase locked loop having a constant loop bandwidth as a function of frequency is described in U.S. Pat. No. 4,313,209 to Drucker, entitled “Phase-Locked Loop Frequency Synthesizer Including Compensated Phase and Frequency Modulation”, the disclosure of which is hereby incorporated herein by reference. Disclosed is a phase locked loop wherein the transfer characteristic of the main loop phase detector is controlled to maintain a constant loop bandwidth. Compensation for carrier frequency-related variations in the gain factors associated with the loop voltage controlled oscillator and compensation for changes in the loop frequency division ratio, as well as compensation for variations caused by frequency-sensitive networks that are embedded in the phase locked loop feedback may be provided. A digital-to-analog converter is responsive to a lookup table, to thereby provide a variable attenuator that is controlled by a parallel format digitally encoded signal, so as to equalize the system for frequency-related variations in the gain factor K
v
of the voltage controlled oscillator.
Unfortunately, the use of a digital-to-analog converter and lookup table to provide constant loop bandwidth may introduce problems in phase locked loops. For example, the lookup table may use an external input to the phase locked loop, which may complicate the design thereof. Moreover, the input to the digital-to-analog converter is generally a digital signal which may use a digital bus, and may thereby introduce noise into the sensitive phase locked loop.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide improved phase locked loops.
It is another object of the invention to provide phase locked loops that can provide constant loop bandwidth as a function of frequency.
It is another object of the present invention to provide phase locked loops that need not use digital circuits and table lookups to provide constant loop bandwidth as a function of frequency.
These and other objects are provided by phase locked loops that include an analog multiplier network, wherein the loop filter and the analog multiplier network are serially connected between the phase detector and the controlled oscillator of the phase locked loop. The analog multiplier network need not use an external input or digital signals from a digital bus. The analog multiplier network can provide an analog linearizer that equalizes the loop bandwidth of the phase locked loop as a function of frequency. More specifically, the analog multiplier network equalizes the loop bandwidth of the phase locked loop as a function of frequency, to provide constant loop bandwidth for the phase locked loop as a function of frequency.
Phase locked loops according to the invention include a controlled oscillator that is responsive to a control signal to generate an output signal. A divider divides the output signal to produce a divided output signal. A phase detector is responsive to a reference frequency input signal and to the divided signal to produce an error signal. A loop filter and an analog multiplier network are provided, wherein the loop filter and the analog multiplier are serially connected between the phase detector and the controlled oscillator.
The loop filter is preferably a two terminal loop filter having a loop filter input terminal and a loop filter output terminal. The analog multiplier network is preferably a two terminal analog multiplier network having an analog multiplier network input terminal and an analog multiplier network output terminal. The loop filter input terminal, the loop filter output terminal, the analog multiplier input terminal and the analog multiplier output terminal are serially connected between the phase detector and the controlled oscillator.
A preferred embodiment of an analog multiplier network comprises an analog multiplier network input node, an analog multiplier output node, first through third multipliers and first through fifth resistors. The first resistor is connected between a supply voltage and the analog multiplier network output node. The second resistor is connected between the analog multiplier network input node and the analog multiplier network output node. The first multiplier and third resistor are serially connected between the analog multiplier network input node and the analog multiplier network output node. The second multiplier

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