Phase-locked loop with sync detector

Details Phase-locked loop with sync detector Phase-locked loop with sync detector

1989-10-31

1993-05-25

Kuntz, Curtis

Pulse or digital communications

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331 1R, 455260, H03D 324

Patent

active

052146774

ABSTRACT:
In a sync detection circuit, an input pulse signal at frequency f.sub.0 is compared with an output pulse signal from a frequency divider to produce a control signal representative of a difference in frequency or phase between the input and output pulse signals. A voltage-controlled oscillator generates pulses at a frequency f.sub.0 .times.N (where N.gtoreq.2) when the control signal indicates that the frequency or phase difference is zero or pulses at a variable frequency when the control signal indicates that the frequency or phase difference is non-zero. The frequency divider divides the frequency of the pulses from the oscillator by a factor N to generate the output pulse signal. A decision circuit is provided for detecting when the pulses generated by the oscillator during an interval between pulses of the input pulse signal are equal to at least N to give an indication that a phase alignment is established between the input and output pulse signals. If N is equal to or greater than 4, the decision circuit may comprise a frequency divider for dividing the frequency of the input pulse signal by a factor M (where M.gtoreq.2) to define the count interval between successive pulses from the second frequency divider, so that phase alignment occurs when MN pulses of the input pulse signal exist between the counte interval.

REFERENCES:
patent: 4791488 (1988-12-01), Fukazawa et al.
patent: 4875108 (1989-10-01), Minuhin et al.
patent: 4933959 (1990-06-01), Kneahtel
patent: 4943788 (1990-07-01), Laws et al.

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