Oscillators – Automatic frequency stabilization using a phase or frequency... – With reference oscillator or source
Reexamination Certificate
2002-03-27
2003-09-16
Kinkead, Arnold (Department: 2817)
Oscillators
Automatic frequency stabilization using a phase or frequency...
With reference oscillator or source
C331S016000, C331S018000, C331S00100A, C327S156000, C327S159000
Reexamination Certificate
active
06621356
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention:
The invention relates to a phase-locked loop which can be used in mobile radio, for example.
The phase-locked loop, also designated as PLL hereinafter, can be used in particular in TDMA mobile radio systems (Time Division Multiple Access) such as, for example, GSM (Global System for Mobile Communication) in multislot operation. Time division multiple access is a method for organized access to a communication medium. The basic idea is to split the available bandwidth uniformly between the individual subscribers. There is a time frame which, in the case of a plurality of subscribers, is subdivided into time slots of equal size, and each subscriber is assigned a time slot. This demands transient recovery times that are shorter than 250 &mgr;s. With a customary integer-N phase-locked loop, however, such a short transient recovery time can barely be achieved.
U.S. patent application Ser. No. 5,694,089 discloses a PLL frequency synthesizer. The synthesizer has a reference divider for dividing the reference signal. Furthermore, it has an RF signal divider that divides the output signal of a voltage-controlled oscillator. If the frequency is changed, first the divider value of the RF signal divider changes periodically by, on average, a fractional divider value. If the frequency has approximately changed over, the RF signal divider is brought into the operating mode of a conventional integer-N divider. For this purpose, the frequency can rapidly be changed over into the fractional operating mode. Consequently —depending on the operating mode—the RF signal divider is loaded with different divider values. However, this has the disadvantage that the transient recovery process is slowed down by virtue of the fact that new divider values have to be loaded into the RF signal divider.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a phase-locked loop which overcomes the above-mentioned disadvantages of the prior art apparatus of this general type.
In particular, it is an object of the invention to provide a phase-locked loop in which the transient recovery duration is very short and the interference signal component is small.
With the foregoing and other objects in view there is provided, in accordance with the invention, a phase-locked loop that includes: a voltage-controlled oscillator for generating an oscillator signal having a frequency; a controllable charge pump having an output connected to the voltage-controlled oscillator; a phase comparator; a first frequency divider which, during a transient recovery duration, generates a first divider output signal by dividing the frequency of the oscillator signal and provides the first divider output signal to the phase comparator; and a unit which, after the transient recovery duration, divides the frequency of the first divider output signal to obtain a divided first divider output signal and provides the divided first divider output signal to the phase comparator. The phase comparator compares the first divider output signal with a first reference signal during the transient recovery duration. The phase comparator compares the divided first divider output signal with a second reference signal after the transient recovery duration. The phase comparator has an output connected to the controllable charge pump.
In accordance with an added feature of the invention, the unit includes a second frequency divider and a first multiplexer with a first input, a second input, and an output. The first frequency divider has an output connected to the first input of the first multiplexer, and the second frequency divider has an output connected to the second input of the first multiplexer.
In accordance with an additional feature of the invention, the phase-locked loop includes: a third frequency divider that receives a reference oscillator signal from a reference oscillator and generates the first reference signal from the reference oscillator signal; and a fourth frequency divider that receives the reference oscillator signal from the reference oscillator and generates the second reference signal from the reference oscillator signal.
In accordance with another feature of the invention, the phase-locked loop includes a second multiplexer that selectively passes either the first reference signal or the second reference signal to the phase comparator.
In accordance with a further feature of the invention, the phase-locked loop includes: a second multiplexer that has a first input and a second input; a third frequency divider that is connected to the first input of the second multiplexer; and a fourth frequency divider that connects the third frequency divider to the second input of the second multiplexer.
In accordance with a further added feature of the invention, the phase-locked loop includes a filter that is connected between the controllable charge pump and the voltage-controlled oscillator.
In accordance with a further additional feature of the invention, the filter is a low-pass filter.
In accordance with yet an added feature of the invention, the unit includes a multiplexer that is controlled by a control device.
In accordance with yet an additional feature of the invention, the phase-locked loop includes a filter that is connected between the controllable charge pump and the voltage-controlled oscillator. The charge pump and the filter have parameters that are prescribed by the control device.
In accordance with yet another feature of the invention, the unit has a first gating circuit for gating the first divider output signal from the first frequency divider; and the unit has a gating logic control circuit for controlling the first gating circuit.
In accordance with yet a further feature of the invention, the gating circuit is an AND gate that has a first input and a second input; the first frequency divider has an output connected to the first input of the AND gate; the gating logic control circuit has an output connected to the second input of the AND gate; and the AND gate has an output connected to the phase comparator.
In accordance with yet a further added feature of the invention, the phase-locked loop includes a second gating circuit for gating a reference signal. The gating logic control circuit controls the second gating circuit.
In accordance with yet a further additional feature of the invention, the phase-locked loop includes a control device that, together with the reference signal, controls the gating logic control circuit.
In accordance with yet another added feature of the invention, the phase-locked loop includes an accumulator for holding a value. The first frequency divider is connected to the accumulator. The first frequency divider depending on the value held in the accumulator, divides the frequency of the oscillator signal by either a first value or a second value.
In other words, the phase-locked loop has a voltage-controlled oscillator, which generates an oscillator signal. Furthermore, a first frequency divider is provided, which divides the frequency of the oscillator signal, generates a first divider output signal therefrom and passes it to a phase comparator during the transient recovery duration of the phase-locked loop. A unit is additionally provided, which, after the transient recovery duration of the phase-locked loop, divides the frequency of the first divider output signal and passes this second divider output signal to the phase comparator. The phase comparator compares the first divider output signal with a first reference signal during the transient recovery duration of the phase-locked loop and compares the second divider output signal with a second reference signal after the transient recovery duration of the phase-locked loop. The output of the phase comparator is connected to a controllable charge pump. The output of the controllable charge pump is connected to the voltage-controlled oscillator.
In an advantageous embodiment of the invention, the unit of the phase-locked loop has a second divider and a first multiplexe
Götz Edmund
Memmler Bernd
Schönleber Günter
Greenberg Laurence A.
Infineon - Technologies AG
Kinkead Arnold
Locher Ralph E.
Stemer Werner H.
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