Phase locked loop with reduced frequency/phase lock time

Details Phase locked loop with reduced frequency/phase lock time Phase locked loop with reduced frequency/phase lock time

1989-12-27

1990-08-21

Mis, David

Oscillators

Automatic frequency stabilization using a phase or frequency...

Tuning compensation

331 1A, 331 25, H03L 718

Patent

active

049510053

ABSTRACT:
A phase locked loop for providing a programmable frequency output signal with reduced phase-frequency lock time. A phase detector detects a phase difference between a reference frequency divided by a first number, and a frequency of the output signal divided by a second number. First and second counters receive the first and the second input numbers to divide a respective frequency. Whenever an input number is loaded, a load signal resets the phase detector and causes each counter to be loaded, which reduces the lock time of the loop.

REFERENCES:
patent: 4378509 (1983-03-01), Hatchett et al.
patent: 4714899 (1987-12-01), Kurtzman et al.

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