Phase locked loop with phase shifted input

Details Phase locked loop with phase shifted input Phase locked loop with phase shifted input

2007-03-14

2009-12-22

Kinkead, Arnold (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Plural a.f.s. for a single oscillator

C331S011000, C327S156000

Reexamination Certificate

active

07636018

ABSTRACT:
In a phase locked loop (PLL), phase shifters shift a phase of an input signal. Based on the phases of the input signal, the shifted signals, and a frequency division output signal, phase frequency detectors (PFDs) generate phase difference signals. In response to the phase difference signals, charge pumps (CPs) control output voltages thereof. Based on the output voltages of the CPs, a voltage controlled oscillator (VCO) outputs an output signal. A frequency divider divides the frequency of the output signal from the VCO to generate the frequency division output signal. A circulator outputs the frequency division output signal to one of the PFDs at a proper timing. A modulator reduces quantization errors of the frequency divider.

REFERENCES:
patent: 5408200 (1995-04-01), Buhler
patent: 6560306 (2003-05-01), Duffy et al.
patent: 6603360 (2003-08-01), Kim et al.
patent: 6901126 (2005-05-01), Gu
patent: 7486145 (2009-02-01), Floyd et al.

Affiliated with

Also associated with

Rating

Phase locked loop with phase shifted input does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Phase locked loop with phase shifted input, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Phase locked loop with phase shifted input will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4140685