Phase-locked loop with pattern controlled bandwidth circuit

Details Phase-locked loop with pattern controlled bandwidth circuit Phase-locked loop with pattern controlled bandwidth circuit

1991-02-26

1991-10-15

Mis, David

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

331 17, 375120, H03L 7089

Patent

active

050577948

ABSTRACT:
An all-digital phase-locked loop (ADPLL) is disclosed having a wide bandwidth while maintaining relatively small steps for phase error correction. A random walk filter with memory and a pattern sensitive phase adjustment circuit cooperate to control the ADPLL frequency/phase adjustment rate by taking multiple, relatively smnall steps in phase error correction at fixed intervals of time. A short cycle occurs when the phase disparity is large, interrupting the execution of the fixed interval cycle expediting the ADPLL phase lock time without sacrificing resolution in the phase error correction steps.

REFERENCES:
patent: 4242639 (1980-12-01), Boone
patent: 4584695 (1986-04-01), Wong et al.
patent: 4712223 (1987-12-01), Nelson
patent: 4712224 (1987-12-01), Nelson
patent: 4733197 (1988-03-01), Chow
patent: 4791386 (1988-12-01), Shiga
patent: 4855683 (1989-08-01), Troudet et al.

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