Phase-locked-loop with noise shaper

Oscillators – Automatic frequency stabilization using a phase or frequency... – With reference oscillator or source

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Details

331 1A, 331 16, 327115, 327156, 327159, 375376, 455260, H03L 706, H03L 718

Patent

active

058252533

ABSTRACT:
A phase lock loop wherein the reference clock is divided by a variable divider which is capable of dividing the reference clock by a divider ratio of 2, 3, 4, . . . or M depending on the value of a control signal. The control signal is generated from a divider controller in response to a controller input. The noise shaping characteristics of the divider controller results in dithering of the variable divider ratios such that the average frequency of the divided reference clock is at the desired comparison frequency but the quantization noise from the fractional divide is pushed from low frequency to high frequency where it is more easily filtered. The noise shaper can be implemented with many bits of resolution to allow for a wide frequency control range and high frequency accuracy. A dither circuit to prevent limit cycling at the output of the noise shaper.

REFERENCES:
patent: 4560960 (1985-12-01), Chanrion

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