Phase locked loop with multiple, programmable, operating frequen

Details Phase locked loop with multiple, programmable, operating frequen Phase locked loop with multiple, programmable, operating frequen

1996-09-11

1998-11-17

Mis, David

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

331175, 327156, H03L 700

Patent

active

058382046

ABSTRACT:
An application specific integrated circuit (ASIC) including a phase-locked loop (PLL) circuit operably coupled to an internal clock and an external clock. The present PLL circuit includes an internal phase detector circuit, an internal charge pump operably coupled to the phase detector circuit, a loop filter operably coupled to the charge pump, and an internal programmable voltage-controlled oscillator 200, 300. The internal programmable voltage controlled oscillator includes a plurality of delay elements, which have a respective switch to turn-on the delay elements. A storage device having a plurality of outputs providing selected switch signals to the voltage oscillator program one of a plurality of center frequencies. Each of the outputs is operably coupled respectively to the delay elements through the respective switch. The switch isolates a first group of delay elements from a second group of delay elements. Setting simultaneous operating (SSO) limits for an application specific integrated circuit (ASIC) having a phase-locked loop sets a limit for the PLL pins.

REFERENCES:
patent: 4517532 (1985-05-01), Neidorff
patent: 4584695 (1986-04-01), Wong et al.
patent: 5075640 (1991-12-01), Miyazawa
patent: 5117206 (1992-05-01), Imamura
patent: 5382921 (1995-01-01), Estrada et al.
patent: 5389898 (1995-02-01), Taketoshi et al.
patent: 5479457 (1995-12-01), Waters

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