Phase locked loop with means for preventing locking at undesired

Details Phase locked loop with means for preventing locking at undesired Phase locked loop with means for preventing locking at undesired

1977-12-29

1979-05-01

Grimm, Siegfried H.

Oscillators

Automatic frequency stabilization using a phase or frequency...

Tuning compensation

331 17, 331 25, H03B 304

Patent

active

041526694

ABSTRACT:
Disclosed is a phase locked loop (PLL) circuit adapted for use, for example, in TV tuners. The PLL circuit has a voltage-controlled type oscillator, program divider, a phase detector and a low-pass filter, as is the case of conventional PLL circuits, and in addition, includes means for making the phase of the variable signal input to the phase detector lag behind the phase of the reference signal when a program switch for determining the divisor number of the program divider and a power source switch are operated, or means are provided at the output side of the low-pass filter for preventing the oscillator from oscillating at a frequency higher than one octave above a preselected frequency. These means are each effective to avoid the locking of the PLL circuit at a frequency which is a multiple of the desired frequency, thereby to ensure a safe and stable operation of the circuit in which the PLL circuit is incorporated.

REFERENCES:
patent: 3903482 (1975-09-01), Pausini et al.
patent: 3921094 (1975-11-01), Schaible
patent: 3939429 (1976-02-01), Lohn et al.
patent: 4011520 (1977-03-01), Schaefer
patent: 4048582 (1977-09-01), Ihara
Alberkrack, "A Phase-Locked Loop Tuning System for Television", Motorola Application Note AN-744, pp. 1-12, (date unknown).

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