Phase locked loop with low steady state phase errors and...

Details Phase locked loop with low steady state phase errors and... Phase locked loop with low steady state phase errors and...

2005-05-24

2005-05-24

Nguyen, Linh My (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S156000

Reexamination Certificate

active

06897691

ABSTRACT:
A phase locked loop (PLL) with low steady state phase errors utilizes a delay unit to delay an input signal or a reference clock so as to lower the steady state phase errors of the PLL. A calibration circuit is used to adjust the delay time of the delay unit and includes a signal generator for generating a simulation input signal and a simulation reference clock according to a phase locked clock; a delay unit for delaying the simulation reference clock and generating a delayed reference clock; a phase detector for detecting the phase error between the simulation input signal and the delayed reference clock and generating charge control signals; a charge pump and an integrator for generating an error voltage according to the charge control signals; a delay time control unit for adjusting the delay time of the delay unit according to the error voltage; and a voltage control oscillator for generating the oscillation clock according to a reference control voltage.

REFERENCES:
patent: 5260842 (1993-11-01), Leake et al.
patent: 5594376 (1997-01-01), McBride et al.
patent: 6236697 (2001-05-01), Fang
patent: 6359950 (2002-03-01), Gossmann et al.

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