Phase locked loop with low power feedback path and method of ope

Details Phase locked loop with low power feedback path and method of ope Phase locked loop with low power feedback path and method of ope

1994-09-06

1995-06-27

Grimm, Siegfried H.

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

331 8, 331 14, 331 25, H03L 707

Patent

active

054283175

ABSTRACT:
A phase locked loop (10) has a first (24) and a second (28) feedback path by which a generated clock signal may be phase and frequency matched to an input reference clock signal. The two feedback paths are delay matched so either one may be used to maintain "PLL lock." However, the first path consumes significantly less power than the second path. Control circuitry (22) selects which path is fed back through a multiplexer (126) and disables the second path when the path is not needed.

REFERENCES:
patent: 5276913 (1994-01-01), Lee et al.

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